公开(公告)号：US20220155539A1

公开(公告)日：2022-05-19

申请号：US16953146

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Sameer PAITAL ,  Sai VADLAMANI ,  Rahul N. MANEPALLI ,  Xiaoqian LI ,  Suresh V. POTHUKUCHI ,  Sujit SHARAN ,  Arnab SARKAR ,  Omkar KARHADE ,  Nitin DESHPANDE ,  Divya PRATAP ,  Jeremy ECTON ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Zhichao ZHANG ,  Kemal AYGÜN ,  Bai NIE ,  Kristof DARMAWIKARTA ,  James E. JAUSSI ,  Jason M. GAMBA ,  Bryan K. CASPER ,  Gang DUAN ,  Rajesh INTI ,  Mozhgan MANSURI ,  Susheel JADHAV ,  Kenneth BROWN ,  Ankar AGRAWAL ,  Priyanka DOBRIYAL

IPC: G02B6/42

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：US20200343175A1

公开(公告)日：2020-10-29

申请号：US16392171

申请日：2019-04-23

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Gang DUAN ,  Kemal AYGÜN ,  Jieying KONG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments include package substrates and methods of forming the package substrates. A package substrate includes a first conductive layer in a first dielectric, a second dielectric over the first dielectric, and a second conductive layer in the second dielectric, where the second conductive layer includes first and second traces. The package substrate also includes a third conductive layer over the second dielectric, and a high dielectric constant (Dk) and low DK regions in the first and second dielectrics, where the high Dk region surrounds the first traces, and where the low Dk region surrounds the second traces. The high Dk region may be between the first and third conductive layers. The low Dk region may be between the first and third conductive layers. The package substrate may include a dielectric region in the first and second dielectrics, where the dielectric region separates the high Dk and low Dk regions.

公开(公告)号：US20250106997A1

公开(公告)日：2025-03-27

申请号：US18373088

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Ehsan ZAMANI ,  Umesh PRASAD ,  Logan MYERS ,  Shayan KAVIANI ,  Darko GRUJICIC ,  Elham TAVAKOLI ,  Mahdi MOHAMMADIGHALENI ,  Rengarajan SHANMUGAM ,  Rachel Guia GIRON ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN

IPC: H05K1/11 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03

Abstract: Embodiments disclosed herein include glass cores with through glass vias (TGVs). In an embodiment, an apparatus comprises a substrate that is a solid glass layer. In an embodiment, an opening is provided through a thickness of the substrate, and a liner with a first surface is on a sidewall of the opening and a second surface is facing away from the sidewall of the opening. In an embodiment, the liner comprises a matrix, and filler particles in the matrix. In an embodiment, a plurality of cavities are provided into the second surface of the liner. In an embodiment, a via is in the opening, where the via is electrically conductive.

公开(公告)号：US20240250043A1

公开(公告)日：2024-07-25

申请号：US18606876

申请日：2024-03-15

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI ,  Rahul MANEPALLI ,  Xiaoying GUO

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

公开(公告)号：US20240222216A1

公开(公告)日：2024-07-04

申请号：US18091034

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Zhixin XIE ,  Jung Kyu HAN ,  Gang DUAN

IPC: H01L23/31 ,  G02B6/42 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/3135 ,  G02B6/4239 ,  H01L21/563 ,  H01L21/565 ,  H01L23/295 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/3201 ,  H01L2224/32054 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate with a die coupled to the package substrate by a plurality of interconnects. In an embodiment, a first layer is on the package substrate surrounding the die, and a second layer is over and around the die. In an embodiment, the second layer underfills the plurality of interconnects, and the second layer has a different material composition than the first layer.

公开(公告)号：US20240213164A1

公开(公告)日：2024-06-27

申请号：US18089483

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Gang DUAN ,  Liang HE ,  Ziyin LIN ,  Elizabeth NOFEN ,  Yiqun BAI ,  Jonathan ATKINS ,  Jesus S. NIETO PESCADOR ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5381 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/14 ,  H01L2224/16104

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, and an opening in the package substrate. In an embodiment, a plurality of first pads are provided at a bottom of the opening, and a bridge die is in the opening. In an embodiment, the bridge die comprises a plurality of second pads that are coupled to the first pads by solder. In an embodiment, a non-conductive film (NCF) is around the solder between the first pads and the second pads.

公开(公告)号：US20240188223A1

公开(公告)日：2024-06-06

申请号：US18060581

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Zhixin XIE ,  Jung Kyu HAN ,  Gang DUAN

IPC: H05K3/28 ,  B29C70/70

CPC classification number: H05K3/284 ,  B29C70/70 ,  B29L2031/3406

Abstract: There may be provided an apparatus. The apparatus may include a first dispensing unit and a second dispensing unit. The apparatus may further include a connection assembly coupled to the first dispensing unit and the second dispensing unit in a manner such that a position of the first dispensing unit or the second dispensing unit relative to the other of said first dispensing unit or second dispensing unit may be adjustable via the connection assembly.

公开(公告)号：US20240071935A1

公开(公告)日：2024-02-29

申请号：US17895965

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08225 ,  H01L2224/80894 ,  H01L2224/80895

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate, where the first substrate comprises glass, and a second substrate over the first substrate, where the second substrate comprises glass. In an embodiment, electrically conductive routing is provided in the second substrate. In an embodiment, a first die is over the second substrate, and a second die is over the second substrate. In an embodiment, the electrically conductive routing electrically couples the first die to the second die.

公开(公告)号：US20240071848A1

公开(公告)日：2024-02-29

申请号：US17895916

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Bai NIE ,  Gang DUAN ,  Kyle ARRINGTON ,  Ziyin LIN ,  Hongxia FENG ,  Yiqun BAI ,  Xiaoying GUO ,  Dingying David XU ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.

公开(公告)号：US20240063203A1

公开(公告)日：2024-02-22

申请号：US17889962

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Navneet SINGH ,  Sushil PADMANABHAN ,  Samarth ALVA

IPC: H01L25/18 ,  H01L23/15 ,  H01L23/538 ,  H01L23/48 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/481 ,  H01L23/5384 ,  H01L21/486 ,  H01L21/4857 ,  H01L25/50 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass, and buildup layers over the first substrate. In an embodiment, a first die is over the buildup layers, a second die is over the buildup layers and adjacent to the first die, and where conductive routing in the buildup layers electrically couples the first die to the second die.