公开(公告)号：US09142533B2

公开(公告)日：2015-09-22

申请号：US12784266

申请日：2010-05-20

申请人： Wen-Wei Shen ,  Ying-Ching Shih ,  Chen-Shien Chen ,  Ming-Fa Chen

发明人： Wen-Wei Shen ,  Ying-Ching Shih ,  Chen-Shien Chen ,  Ming-Fa Chen

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L21/486 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0381 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/1162 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1354 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2224/05552 ,  H01L2924/00

摘要： A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.

摘要翻译： 提供了可用于将一个衬底互连到另一衬底的凸块结构。 导电柱形成在第一基板上，使得导电柱的宽度不同于第二基板上的接触表面。 在一个实施例中，第一基板的导电柱具有梯形形状或具有锥形侧壁的形状，从而提供具有比尖端部宽的基部的导电柱。 基板可以各自为集成电路管芯，插入件，印刷电路板，高密度互连等。

公开(公告)号：US08859424B2

公开(公告)日：2014-10-14

申请号：US12840903

申请日：2010-07-21

申请人： Yung-Jean Lu ,  Ming-Fa Chen ,  Chen-Shien Chen ,  Jao Sheng Huang

发明人： Yung-Jean Lu ,  Ming-Fa Chen ,  Chen-Shien Chen ,  Jao Sheng Huang

IPC分类号： H01L21/44 ,  H01L21/683

CPC分类号： H01L21/6833 ,  Y10T29/49124

摘要： A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.

摘要翻译： 公开了一种用于半导体晶片载体的系统和方法。 一个实施方案包括半导体晶片载体，其中将导电掺杂剂注入到载体中，以便放大静电卡盘和载体之间的库仑力，以补偿由较薄的半导体晶片产生的减小的力。 另一个实施例在载体内形成导电层和通孔，而不是注入导电掺杂剂。

公开(公告)号：US08501587B2

公开(公告)日：2013-08-06

申请号：US12613408

申请日：2009-11-05

申请人： Ming-Fa Chen ,  Jao Sheng Huang

发明人： Ming-Fa Chen ,  Jao Sheng Huang

IPC分类号： H01L21/467 ,  H01L21/441

CPC分类号： H01L23/49816 ,  H01L21/76898 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

摘要翻译： 描述形成叠层半导体芯片的结构和方法。 在一个实施例中，形成半导体芯片的方法包括从第一基板的顶表面形成用于贯通基板通孔的开口。 开口的侧壁衬有绝缘衬垫，开口填充有导电填充材料。 第一衬底从相对的底表面蚀刻以形成突起，突起被绝缘衬垫覆盖。 抗蚀剂层沉积在突起周围以暴露绝缘衬垫的一部分。 蚀刻暴露的绝缘衬垫以沿突起形成侧壁间隔物。

公开(公告)号：US08158456B2

公开(公告)日：2012-04-17

申请号：US12329341

申请日：2008-12-05

申请人： Ming-Fa Chen ,  Chen-Shien Chen ,  Wen-Chih Chiu

发明人： Ming-Fa Chen ,  Chen-Shien Chen ,  Wen-Chih Chiu

IPC分类号： H01L21/02

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00

摘要： The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to metallization processing. TSVs may be fabricated with increased aspect ratio, extending deeper in a wafer substrate. The method generally reduces the risk of overly-thinning a wafer substrate in a wafer back-side grinding process typically used to expose and make electrical contacts to the TSVs. By providing deeper TSVs and bonding pads, individual wafers and dies may be bonded directly between the TSVs and bonding pads on an additional wafer.

摘要翻译： 描述了在集成电路（IC）裸片或晶片中通过硅通孔（TSV）的形成，其中在金属化处理之前的集成工艺中形成TSV。 TSV可以以增加的纵横比制造，在晶片衬底中更深地延伸。 该方法通常降低了通常用于暴露并与TSV的电接触的晶片背面研磨工艺中的晶片衬底过度稀化的风险。 通过提供更深的TSV和接合焊盘，单个晶片和管芯可以直接接合在TSV和附加晶片上的焊盘之间。

公开(公告)号：US20110291232A1

公开(公告)日：2011-12-01

申请号：US12791705

申请日：2010-06-01

申请人： Hsiao-Tsung Yen ,  Chin-Wei Kuo ,  Hsien-Pin Hu ,  Sally Liu ,  Ming-Fa Chen ,  Jhe-Ching Lu

发明人： Hsiao-Tsung Yen ,  Chin-Wei Kuo ,  Hsien-Pin Hu ,  Sally Liu ,  Ming-Fa Chen ,  Jhe-Ching Lu

IPC分类号： H01L29/86 ,  H01F5/00 ,  H01L21/50

CPC分类号： H01L23/5227 ,  H01F17/0013 ,  H01F27/2804 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00 ,  H01L2224/0401

摘要： In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.

摘要翻译： 根据实施例，半导体器件包括半导体管芯，插入件和将半导体管芯接合到插入件的导电凸块。 半导体管芯包括第一金属化层，第一金属化层包括第一导电图案。 插入器包括第二金属化层，并且第二金属化层包括第二导电图案。 一些导电凸块将第一导电图案电耦合到第二导电图案以形成线圈。 其他实施例考虑了线圈，电感器和/或变压器的其他配置，并考虑了制造方法。

公开(公告)号：US20110248404A1

公开(公告)日：2011-10-13

申请号：US12756727

申请日：2010-04-08

申请人： Ming-Yen Chiu ,  Hsien-Wei Chen ,  Ming-Fa Chen ,  Shin-Puu Jeng

发明人： Ming-Yen Chiu ,  Hsien-Wei Chen ,  Ming-Fa Chen ,  Shin-Puu Jeng

IPC分类号： H01L23/48

CPC分类号： H01L23/522 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05075 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06515 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/14181 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A device includes a semiconductor substrate including a front side and a backside. A through-substrate via (TSV) penetrates the semiconductor substrate. A dummy metal line is formed on the backside of the semiconductor substrate, and may be connected to the dummy TSV.

摘要翻译： 一种器件包括包括正面和背面的半导体衬底。 贯穿衬底通孔（TSV）穿透半导体衬底。 虚拟金属线形成在半导体衬底的背面，并且可以连接到虚拟TSV。

公开(公告)号：US20110193221A1

公开(公告)日：2011-08-11

申请号：US12774558

申请日：2010-05-05

申请人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

发明人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC分类号： H01L23/538 ,  H01L21/60 ,  H01L21/50 ,  H01L23/488

CPC分类号： H01L23/5389 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/81 ,  H01L2924/00012

摘要： A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

摘要翻译： 一种装置包括插入件，其包括具有顶表面的基板。 互连结构形成在衬底的顶表面上，其中互连结构包括至少一个电介质层，以及至少一个电介质层中的金属特征。 多个穿通基板通孔（TSV）在基板中并电耦合到互连结构。 第一个模具结束并粘贴到插入器上。 第二管芯被结合到插入件上，其中第二管芯在互连结构之下。

公开(公告)号：US20110133335A1

公开(公告)日：2011-06-09

申请号：US13028655

申请日：2011-02-16

申请人： Ming-Fa Chen

发明人： Ming-Fa Chen

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L21/7682 ,  H01L23/481 ,  H01L23/5222 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the liner, which is subsequently removed to form an air gap around the conductive material of the through-silicon via. A dielectric layer is formed of the backside of the semiconductor substrate to seal the air gap.

摘要翻译： 提供一种半导体衬底，其具有穿过硅通孔和半导体衬底之间的气隙的通硅通孔。 部分地通过半导体衬底形成开口。 开口首先用衬里衬里，然后开口填充有导电材料。 半导体衬底的背面被薄化以暴露衬里，衬垫随后被去除以在通过硅通孔的导电材料周围形成气隙。 电介质层由半导体衬底的背面形成以密封气隙。

公开(公告)号：US20100178761A1

公开(公告)日：2010-07-15

申请号：US12613408

申请日：2009-11-05

申请人： Ming-Fa Chen ,  Jao Sheng Huang

发明人： Ming-Fa Chen ,  Jao Sheng Huang

IPC分类号： H01L21/768

CPC分类号： H01L23/49816 ,  H01L21/76898 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

摘要翻译： 描述形成叠层半导体芯片的结构和方法。 在一个实施例中，形成半导体芯片的方法包括从第一基板的顶表面形成用于贯通基板通孔的开口。 开口的侧壁衬有绝缘衬垫，开口填充有导电填充材料。 第一衬底从相对的底表面蚀刻以形成突起，突起被绝缘衬垫覆盖。 抗蚀剂层沉积在突起周围以暴露绝缘衬垫的一部分。 蚀刻暴露的绝缘衬垫以沿突起形成侧壁间隔物。

公开(公告)号：US20100171223A1

公开(公告)日：2010-07-08

申请号：US12348650

申请日：2009-01-05

申请人： Chen-Cheng Kuo ,  Chih-Hua Chen ,  Ming-Fa Chen ,  Chen-Shien Chen

发明人： Chen-Cheng Kuo ,  Chih-Hua Chen ,  Ming-Fa Chen ,  Chen-Shien Chen

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having one or more through-silicon vias (TSVs) is provided. The TSVs are formed such that sidewalls of the TSVs have a scalloped surface. In an embodiment, the sidewalls of the TSVs are sloped wherein a top and bottom of the TSVs have different dimensions. The TSVs may have a V-shape wherein the TSVs have a wider dimension on a circuit side of the substrate, or an inverted V-shape wherein the TSVs have a wider dimension on a backside of the substrate. The scalloped surfaces of the sidewalls and/or sloped sidewalls allow the TSVs to be more easily filled with a conductive material such as copper.

摘要翻译： 提供了具有一个或多个穿硅通孔（TSV）的半导体器件。 TSV形成为使得TSV的侧壁具有扇形表面。 在一个实施例中，TSV的侧壁是倾斜的，其中TSV的顶部和底部具有不同的尺寸。 TSV可以具有V形，其中TSV在衬底的电路侧具有更宽的尺寸，或者是倒V形，其中TSV在衬底的背面具有更宽的尺寸。 侧壁和/或倾斜侧壁的扇形表面允许TSV更容易地用诸如铜的导电材料填充。