公开(公告)号：US20160056226A1

公开(公告)日：2016-02-25

申请号：US14468035

申请日：2014-08-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang

IPC: H01L49/02 ,  H01L23/00

CPC classification number: H01L23/5225 ,  H01L23/3114 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11334 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/19015 ,  H01L2924/19042 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Some novel features pertain to an integrated device that includes a substrate, several lower level metal layers, several lower level dielectric layers, and a redistribution portion. The redistribution portion includes a first dielectric layer that includes a first dielectric thickness, and an electromagnetic (EM) passive device that includes a first redistribution interconnect. The first redistribution interconnect includes a first redistribution thickness, where the first dielectric thickness is at least about 2 times greater than the first redistribution thickness. In some implementations, the redistribution portion includes a radio frequency (RF) shield. In some implementations, the RF shield is located between a passivation layer and the several lower level dielectric layers. The RF shield is located between the EM passive device and the several lower level dielectric layers. The RF shield is electrically coupled to an interconnect configured to provide an electrical path for a ground signal.

Abstract translation: 一些新颖的特征涉及一种集成器件，其包括衬底，多个下层金属层，几个下层电介质层和再分配部分。 再分配部分包括包括第一电介质厚度的第一电介质层和包括第一再分布互连的电磁（EM）无源器件。 第一再分配互连包括第一再分布厚度，其中第一介电厚度比第一再分布厚度大至少约2倍。 在一些实现中，再分配部分包括射频（RF）屏蔽。 在一些实施方案中，RF屏蔽位于钝化层和多个较低级别的介电层之间。 RF屏蔽位于EM无源器件和几个较低级别的介电层之间。 RF屏蔽电耦合到被配置为提供用于接地信号的电路径的互连。

公开(公告)号：US20160055976A1

公开(公告)日：2016-02-25

申请号：US14468212

申请日：2014-08-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang

IPC: H01G4/30 ,  H01L21/768 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248 ,  H01L23/522 ,  H01G4/012

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248 ,  H01L21/76802 ,  H01L21/7687 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated devices include a substrate, and a capacitor embedded within the substrate. The capacitor is configured to include a first electrode disposed on a first surface, a second electrode disposed on an opposing second surface, and a plurality of capacitor plates extending transverse between the first electrode and the second electrode. Each capacitor plate is electrically coupled to one of the first electrode or the second electrode. A plurality of vias are positioned to extend through the substrate to one of the first electrode or the second electrode. Other aspects, embodiments, and features are also included.

Abstract translation: 集成器件包括衬底和嵌入衬底内的电容器。 电容器被配置为包括设置在第一表面上的第一电极，设置在相对的第二表面上的第二电极和在第一电极和第二电极之间横向延伸的多个电容器板。 每个电容器板电耦合到第一电极或第二电极之一。 定位多个通孔以将基板延伸到第一电极或第二电极之一。 还包括其他方面，实施例和特征。

公开(公告)号：US20150115403A1

公开(公告)日：2015-04-30

申请号：US14063934

申请日：2013-10-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Mario Francisco Velez ,  Chengjie Zuo ,  Changhan Hobie Yun

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

Abstract translation: 一些新颖的特征涉及包括衬底，通过衬底的第一腔和围绕衬底的第一腔配置的环形电感器的集成器件。 环形电感器包括围绕第一腔配置的一组绕组。 该组绕组包括在衬底的第一表面上的第一组互连，一组通过衬底通孔（TSV）和在衬底的第二表面上的第二组互连。 第一组互连通过集合TSV耦合到第二组互连。 在一些实施方案中，集成器件还包括位于第一腔内的互连材料（例如，焊球）。 互连材料被配置为将管芯耦合到印刷电路板。 在一些实施方案中，互连材料是环形电感器的一部分。

公开(公告)号：US20140266508A1

公开(公告)日：2014-09-18

申请号：US13835211

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Changhan Hobie Yun ,  Dong Wook Kim

IPC: H03H7/01 ,  H03H3/00 ,  H01G4/40

CPC classification number: H03H7/0115 ,  H01G4/40 ,  H03H3/00 ,  H03H7/12 ,  H05K1/162 ,  H05K2201/09236 ,  Y10T29/43 ,  Y10T29/49016

Abstract: A planar capacitor includes, in part, a first metal line forming spiral-shaped loops around one of its end point, and a second metal line forming spiral-shaped loops between the loops of the first metal line. The first and second metal lines are coplanar, formed on an insulating layer, and form the first and second plates of the planar capacitor. The planar capacitor may be used to form a filter. Such a filter includes a first metal line forming first spiral-shaped loops, a second metal line forming second spiral-shaped loops, and a third metal line—coplanar with the first and second metal lines—forming loops between the loops of the first and second metal lines. The filter further includes a first inductor coupled between the first and third metal lines, and a second inductor coupled between the second and third metal lines.

Abstract translation: 平面电容器部分地包括围绕其端点之一形成螺旋形环的第一金属线和在第一金属线的环之间形成螺旋形环的第二金属线。 第一和第二金属线是共面的，形成在绝缘层上，并形成平面电容器的第一和第二板。 平面电容器可以用于形成滤波器。 这种过滤器包括形成第一螺旋形环的第一金属线，形成第二螺旋状环的第二金属线和与第一和第二金属线形成环之间的第一和第二金属线形成环的第三金属线 - 共面， 第二条金属线。 滤波器还包括耦合在第一和第三金属线之间的第一电感器和耦合在第二和第三金属线之间的第二电感器。

公开(公告)号：US10304623B2

公开(公告)日：2019-05-28

申请号：US15002174

申请日：2016-01-20

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  John Jong Hoon Lee ,  Sangjo Choi

IPC: G06F1/16 ,  H01F29/02 ,  G05B19/10 ,  H01F27/29 ,  H01F27/42 ,  H05K7/14 ,  H01L23/498 ,  H01L23/64 ,  H01L23/31

Abstract: Some features pertain to a package substrate that includes at least one dielectric layer, an inductor in the at least one dielectric layer, a first terminal coupled to the inductor, a second terminal coupled to the inductor, and a third terminal coupled to the inductor. The first terminal is configured to be a first port for the inductor. The second terminal is configured to be a second port for the inductor. The third terminal is a dummy terminal. In some implementations, the package substrate includes a solder resist layer over the dielectric layer, where the solder resist layer covers the third terminal. In some implementations, the package substrate includes a solder interconnect over the third terminal, such that the solder resist layer is between the third terminal and the solder interconnect. In some implementations, the package substrate is coupled to a die comprising a plurality of switches.

公开(公告)号：US09691694B2

公开(公告)日：2017-06-27

申请号：US14703290

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Xiaonan Zhang ,  Mario Francisco Velez

IPC: H01L23/48 ,  H01L21/336 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/50

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15311

Abstract: An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

公开(公告)号：US09659850B2

公开(公告)日：2017-05-23

申请号：US14563854

申请日：2014-12-08

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/16 ,  H01L23/66 ,  H01L23/482 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/4824 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/66 ,  H01L24/83 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/162 ,  H01L2924/00

Abstract: A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects.

公开(公告)号：US09628052B2

公开(公告)日：2017-04-18

申请号：US14249189

申请日：2014-04-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/50 ,  H03K3/013 ,  H05K1/18 ,  H05K1/03 ,  H05K3/46 ,  G05F3/08 ,  H05K3/30 ,  H01L23/498 ,  H01L23/00

CPC classification number: H03K3/013 ,  G05F3/08 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/183 ,  H05K1/184 ,  H05K3/306 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/49139 ,  H01L2924/00

Abstract: An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network.

公开(公告)号：US09490226B2

公开(公告)日：2016-11-08

申请号：US14462265

申请日：2014-08-18

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Dong Wook Kim ,  Kyu-Pyung Hwang

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/34 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L24/17 ,  H01L21/4857 ,  H01L23/34 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83104 ,  H05K1/0207 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer.

Abstract translation: 本文提供了一种集成器件，其包括衬底，管芯，位于衬底和管芯之间的散热层和被配置为将管芯耦合到散热层的第一互连。 散热层可以被配置成为接地信号提供电路径。 第一互连可以被进一步配置成将热量从管芯传导到散热层。 集成器件还可以包括配置成将管芯耦合到衬底的第二互连。 第二互连可以被进一步配置为在管芯和衬底之间传导功率信号。 集成器件还可以包括位于散热层和衬底之间的介电层，以及位于管芯和散热层之间的阻焊层。

公开(公告)号：US09373583B2

公开(公告)日：2016-06-21

申请号：US14323907

申请日：2014-07-03

Applicant: QUALCOMM Incorporated

Inventor： Jong-Hoon Lee ,  Young Kyu Song ,  Jung Ho Yoon ,  Uei Ming Jow ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L27/08 ,  H01L23/522 ,  H01L49/02 ,  H01L23/64 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L23/00 ,  H01L25/03 ,  H01L23/525

CPC classification number: H01L23/5227 ,  H01L23/5223 ,  H01L23/525 ,  H01L23/645 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81447 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/15788 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die.

Abstract translation: 一些实施方案提供了包括电容器和电感器的集成器件。 电感器电耦合到电容器。 电感器和电容器被配置为在集成器件中用作电信号的滤波器。 电感器包括印刷电路板（PCB）的第一金属层，耦合到PCB的一组焊球，以及模具中的第二金属层。 在一些实施方案中，电容器位于管芯中。 在一些实现中，电容器是PCB上的表面安装无源器件。 在一些实施方案中，第一金属层是PCB上的痕迹。 在一些实施方案中，电感器包括管芯中的第三金属层。 在一些实施方案中，第二金属层是管芯的凸块下金属化（UBM）层，第三金属是管芯的再分布层。