公开(公告)号：US5543584A

公开(公告)日：1996-08-06

申请号：US843684

申请日：1992-02-28

申请人： Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

发明人： Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/498 ,  H01L23/52 ,  H01L23/525 ,  H01L23/538 ,  H05K3/00 ,  H05K3/02 ,  H05K3/22 ,  H05K3/34 ,  H05K1/11

CPC分类号： H01L21/76892 ,  H01L23/49866 ,  H01L23/525 ,  H05K3/225 ,  H01L2924/0002 ,  H05K2201/10181 ,  H05K2201/10234 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2203/0769 ,  H05K2203/107 ,  H05K2203/121 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/0017 ,  H05K3/027 ,  H05K3/34 ,  Y10T29/49124

摘要： The present invention relates generally to a new method of repairing electrical lines, and more particularly to repairing electrical lines having an opening at the module level with devices in place. Various methods and processes are used to repair this open or defective portion in an electrical conductor line. It could be repaired by securing a jumper wire or nugget across the open or the repair could be made by a deposition process, which includes but is not limited to filling the opening with a solder type material or inserting a solder coated electrical wire and heating the solder and allowing the solder to melt and repair the open. One of the attributes of this invention is the ability to repair on a substrate or module on which active components such as chips, and passive components such as pins, capacitors, etc. have been attached. The invention also allows repair of fine line patterns which are normally not repairable by conventional techniques.

摘要翻译： 本发明一般涉及一种修复电线的新方法，更具体地说，涉及在装置的适当位置修复具有模块级开口的电线。 使用各种方法和过程来修复电导体线中的这个开路或有缺陷的部分。 它可以通过将跨接线或熔核固定在整个开口处进行修复，或者可以通过沉积工艺进行修复，该沉积工艺包括但不限于用焊料型材料填充开口或插入焊料涂覆的电线并加热 焊接并允许焊料熔化并修复开路。 本发明的一个特征是在其上附着有诸如引脚，电容器等的诸如芯片和无源部件的有源部件的基板或模块上进行修复的能力。 本发明还允许修复通常不能通过常规技术修复的细线图案。

公开(公告)号：US5153408A

公开(公告)日：1992-10-06

申请号：US607969

申请日：1990-10-31

申请人： Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

发明人： Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/498 ,  H01L23/52 ,  H01L23/525 ,  H01L23/538 ,  H05K3/00 ,  H05K3/02 ,  H05K3/22 ,  H05K3/34

CPC分类号： H01L21/76892 ,  H01L23/49866 ,  H01L23/525 ,  H05K3/225 ,  H01L2924/0002 ,  H05K2201/10181 ,  H05K2201/10234 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2203/0769 ,  H05K2203/107 ,  H05K2203/121 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/0017 ,  H05K3/027 ,  H05K3/34 ,  Y10T29/49124

摘要： The present invention relates generally to a new method of repairing electrical lines, and more praticularly to repairing electrical lines having an open at the module level with devices in place. Various methods and processes are used to repair this open or defective portion in an electrical conductor line. It could be repaired by securing a jumper wire or nugget across the open or the repair could be made by a deposition process, which includes but is not limited to filling the open with a solder type material or inserting a solder coated electrical wire and heating the solder and allowing the solder to melt and repair the open. One of the attributes of this invention is the ability to repair on a substrate or module on which active components such as chips, and passive components such as pins, capacitors, etc. have been attached. The invention also allows repair of fine line patterns which are normally not repairable by conventional techniques.

摘要翻译： 本发明一般涉及一种修复电线的新方法，并且更具体地涉及在装置就位时修复在模块级具有开路的电线。 使用各种方法和过程来修复电导体线中的这个开路或有缺陷的部分。 它可以通过将跨接线或熔核固定在开口处进行修复，或者可以通过沉积工艺进行修复，该沉积工艺包括但不限于用焊料型材料填充开口或插入焊料涂覆的电线并加热 焊接并允许焊料熔化并修复开路。 本发明的一个特征是在其上附着有诸如引脚，电容器等的诸如芯片和无源部件的有源部件的基板或模块上进行修复的能力。 本发明还允许修复通常不能通过常规技术修复的细线图案。

公开(公告)号：US07806341B2

公开(公告)日：2010-10-05

申请号：US12348364

申请日：2009-01-05

申请人： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D. Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

发明人： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D. Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

IPC分类号： G06K19/05

CPC分类号： G06K19/07381 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L23/576 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/3011 ,  H05K1/0275 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/10151

摘要： A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

摘要翻译： 防篡改集成电路（IC）模块包括陶瓷芯片载体; 一个或多个集成电路芯片，附接到芯片载体的顶表面; 一个陶瓷基帽结构，附着在芯片载体的顶表面上，并覆盖一个或多个集成电路芯片; 以及嵌入在所述芯片载体和所述盖结构内的导电栅格结构，所述导电栅格结构具有设置在x方向，y方向和z方向上的多个曲折线; 其中所述导电栅格结构被配置为检测穿透所述IC模块的尝试。

公开(公告)号：US06548909B2

公开(公告)日：2003-04-15

申请号：US09825512

申请日：2001-04-03

申请人： Peter J. Brofman ,  Sudipta K. Ray ,  Kathleen A. Stalter

发明人： Peter J. Brofman ,  Sudipta K. Ray ,  Kathleen A. Stalter

IPC分类号： H01L2144

CPC分类号： H01L24/81 ,  H01L23/49827 ,  H01L2224/13147 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3511 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/10378 ,  H01L2924/00

摘要： A method of interconnecting electronic components by using a plurality of conductive studs on a surface of a first electronic component and a plurality of corresponding conductive vias on the surface of a second electronic component. Camber on the surface of electronic components may be overcome by coating the surface with a dielectric, planarizing the dielectric, and forming conductive vias corresponding to the contact pads thereon. The conductive studs are substantially lead-free and preferably comprise of copper.

摘要翻译： 一种通过使用第一电子部件的表面上的多个导电柱和在第二电子部件的表面上的多个对应的导电通孔来互连电子部件的方法。 可以通过用电介质涂覆表面来平衡电介质，并形成对应于其上的接触焊盘的导电通孔来克服电子部件表面上的弯曲。 导电柱基本上是无铅的，优选地包括铜。

公开(公告)号：US06350625B1

公开(公告)日：2002-02-26

申请号：US09753272

申请日：2000-12-28

申请人： Mitchell S. Cohen ,  William K. Hogan ,  Sudipta K. Ray ,  James L. Speidell ,  S. Jay Chey ,  Steven A. Cordes

发明人： Mitchell S. Cohen ,  William K. Hogan ,  Sudipta K. Ray ,  James L. Speidell ,  S. Jay Chey ,  Steven A. Cordes

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L33/486 ,  H01L33/62 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/30107 ,  H01S5/02268 ,  H01S5/02272 ,  H01S5/02284 ,  H01S5/183

摘要： A novel optoelectronic packaging submount arrangement which incorporates a 90° C. electrical conductor turn, and more specifically methods of producing optoelectronic packaging submount arrangement incorporating 90° C. electrical conductor turns.

摘要翻译： 一种新颖的光电封装基座装置，其结合了90 C.电导体转弯，更具体地说，制造了包含90 C.电导线的光电封装基座装置的方法

公开(公告)号：US06220499B1

公开(公告)日：2001-04-24

申请号：US09163150

申请日：1998-09-29

申请人： Peter J. Brofman ,  Shaji Faroog ,  John U. Knickerbocker ,  Scott I. Langenthal ,  Sudipta K. Ray ,  Kathleen A. Stalter

发明人： Peter J. Brofman ,  Shaji Faroog ,  John U. Knickerbocker ,  Scott I. Langenthal ,  Sudipta K. Ray ,  Kathleen A. Stalter

IPC分类号： B23K3100

CPC分类号： H01L21/67144 ,  H01L21/4853 ,  H01L24/81 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13144 ,  H01L2224/81136 ,  H01L2224/81138 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2203/0278 ,  Y02P70/613 ,  H01L2924/00

摘要： A semiconductor device having C-4 solder connections is joined to a chip carrier having pads suitable for receiving the C-4 solder connections. Sacrificial solder is formed on the chip carrier pads and then planarized to result in a good, planar surface profile for joining to the semiconductor device.

摘要翻译： 具有C-4焊接连接的半导体器件被连接到具有适于接收C-4焊料连接的焊盘的芯片载体。 牺牲焊料形成在芯片载体焊盘上，然后被平坦化以产生用于接合到半导体器件的良好的平坦表面轮廓。

公开(公告)号：US4576659A

公开(公告)日：1986-03-18

申请号：US446300

申请日：1982-12-02

申请人： Robert K. Lewis ,  Sudipta K. Ray

发明人： Robert K. Lewis ,  Sudipta K. Ray

IPC分类号： H01L21/60 ,  B23K35/38 ,  C23C26/00 ,  H01L21/48 ,  H05K1/03 ,  H05K1/09 ,  H05K3/22 ,  H05K3/24 ,  H05K3/34 ,  B23K31/02 ,  C21D1/74

CPC分类号： H01L24/05 ,  B23K35/383 ,  C23C26/00 ,  H01L21/4846 ,  H01L24/03 ,  H05K3/22 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K1/0306 ,  H05K1/09 ,  H05K2201/0317 ,  H05K2203/0315 ,  H05K2203/087 ,  H05K2203/1105 ,  H05K2203/1157 ,  H05K3/244 ,  H05K3/341 ,  H05K3/3489 ,  Y10T428/12528 ,  Y10T428/12889 ,  Y10T428/12903

摘要： The formation of metal oxide contaminants on the surfaces of thin metal films by out-diffusion primarily through the grain boundaries thereof of metal from an underlayer is inhibited by conducting heat cycling of such layered metal structures in an ambient gas mixture composed of inert gas, such as nitrogen, containing a sufficient amount of active gas, such as, hydrogen, carbon monoxide, or the like, substantially to suppress such out-diffusion.

摘要翻译： 金属氧化物污染物在金属薄膜的表面上的形成通过主要通过其从底层的金属的晶粒边界扩散而在金属薄膜的表面上的形成受到这种层状金属结构在由惰性气体组成的环境气体混合物中的热循环的抑制， 作为氮气，含有足够量的活性气体，例如氢气，一氧化碳等，基本上抑制这种扩散。

公开(公告)号：US20110151627A1

公开(公告)日：2011-06-23

申请号：US12642479

申请日：2009-12-18

申请人： Richard S. Graf ,  Thomas E. Lombardi ,  Sudipta K. Ray ,  David J. West

发明人： Richard S. Graf ,  Thomas E. Lombardi ,  Sudipta K. Ray ,  David J. West

IPC分类号： H01L21/60 ,  H05K1/11

CPC分类号： H05K3/3436 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/1413 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14179 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3511 ,  H05K2201/09136 ,  H05K2201/094 ,  H05K2201/10674 ,  H05K2203/048 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81805

摘要： An apparatus, system, and method are disclosed for connecting an integrated circuit device to a substrate. A plurality of standard diameter pillars and three or more increased diameter pillars are disposed on an integrated circuit device. The increased diameter pillars have a diameter that is greater than the standard diameter pillars and a height that is similar to the standard diameter pillars. The standard diameter pillars and the increased diameter pillars form a pattern on the integrated circuit device that corresponds to contact pads on a substrate opposite the integrated circuit device. A first group of solder bumps is disposed between the standard diameter pillars and the contact pads. A second group of solder bumps is disposed between the increased diameter pillars and the contact pads. The second group of solder bumps has pre-connection heights that are greater than pre-connection heights of the first group of solder bumps.

摘要翻译： 公开了用于将集成电路器件连接到衬底的装置，系统和方法。 多个标准直径柱和三个或更多个增加直径的柱布置在集成电路装置上。 增加直径的支柱具有大于标准直径柱的直径和类似于标准直径柱的高度。 标准直径柱和增加的直径柱在集成电路器件上形成对应于与集成电路器件相对的衬底上的接触焊盘的图案。 第一组焊料凸点设置在标准直径柱和接触垫之间。 第二组焊料凸点设置在增加直径的支柱和接触垫之间。 第二组焊料凸块的预连接高度大于第一组焊料凸点的预连接高度。

公开(公告)号：US20090145973A1

公开(公告)日：2009-06-11

申请号：US12348364

申请日：2009-01-05

申请人： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D. Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

发明人： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D. Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

IPC分类号： G06K19/06

CPC分类号： G06K19/07381 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L23/576 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/3011 ,  H05K1/0275 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/10151

摘要： A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

摘要翻译： 防篡改集成电路（IC）模块包括陶瓷芯片载体; 一个或多个集成电路芯片，附接到芯片载体的顶表面; 一个陶瓷基帽结构，附着在芯片载体的顶表面上，并覆盖一个或多个集成电路芯片; 以及嵌入在所述芯片载体和所述盖结构内的导电栅格结构，所述导电栅格结构具有设置在x方向，y方向和z方向上的多个曲折线; 其中所述导电栅格结构被配置为检测穿透所述IC模块的尝试。

公开(公告)号：US06762119B2

公开(公告)日：2004-07-13

申请号：US09885791

申请日：2001-06-20

申请人： Sudipta K. Ray ,  Mitchell S. Cohen ,  Lester Wynn Herron ,  Mario J. Interrante ,  Thomas E. Lombardi ,  Subhash L. Shinde

发明人： Sudipta K. Ray ,  Mitchell S. Cohen ,  Lester Wynn Herron ,  Mario J. Interrante ,  Thomas E. Lombardi ,  Subhash L. Shinde

IPC分类号： H01L2144

CPC分类号： H01S5/02272 ,  G02B6/4238 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01S5/02236 ,  H01S5/02268 ,  H01L2924/00 ,  H01L2924/00014

摘要： A process and structure for forming an optical subassembly in an integrated circuit, comprising: defining electrically conducting lines and bonding pads in a metallization layer on a substrate; depositing a passivation layer over the metallization layer; etching the passivation layer to remove the passivation layer from each of the bonding pads and a portion of the metallization layer associated with each of the bonding pads; diffusing Cr from the lines proximate said bonding pads to prevent solder wetting down lines; bonding an optical device to one of the bonding pads; and attaching the substrate to a carrier utilizing solder bond attachment.

摘要翻译： 一种用于在集成电路中形成光学子组件的工艺和结构，包括：在衬底上的金属化层中限定导电线和焊盘; 在所述金属化层上沉积钝化层; 蚀刻钝化层以从每个接合焊盘和与每个焊盘相关联的金属化层的一部分去除钝化层; 从靠近所述接合焊盘的线扩散Cr，以防止焊料向下润湿; 将光学器件接合到所述接合焊盘之一; 以及使用焊料粘合附着将衬底附接到载体上。