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    Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out Package
    14.
    发明申请
    Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out Package 有权
    半导体器件和在扇出封装中形成精细间距RDL超半导体管芯的方法

    公开(公告)号：US20150179570A1

    公开(公告)日：2015-06-25

    申请号：US14139614

    申请日：2013-12-23

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Pandi C. Marimuthu ,  Yaojian Lin ,  Won Kyoung Choi ,  Il Kwon Shim

    IPC: H01L23/522 ,  H01L25/065 ,  H01L21/56

    CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate. The conductive traces are formed with a narrow pitch. A first semiconductor die and second semiconductor die are disposed over the first conductive layer. A first encapsulant is deposited over the first and second semiconductor die. The substrate is removed. A second encapsulant is deposited over the first encapsulant. A build-up interconnect structure is formed over the first conductive layer and second encapsulant. The build-up interconnect structure includes a second conductive layer. A first passive device is disposed in the first encapsulant. A second passive device is disposed in the second encapsulant. A vertical interconnect unit is disposed in the second encapsulant. A third conductive layer is formed over second encapsulant and electrically connected to the build-up interconnect structure via the vertical interconnect unit.

    Abstract translation: 半导体器件具有包括多个导电迹线的第一导电层。 第一导电层形成在衬底上。 导电迹线以窄间距形成。 第一半导体管芯和第二半导体管芯设置在第一导电层上。 第一密封剂沉积在第一和第二半导体管芯上。 去除衬底。 第二密封剂沉积在第一密封剂上。 在第一导电层和第二密封剂上形成积层互连结构。 积层互连结构包括第二导电层。 第一无源器件设置在第一密封剂中。 第二无源器件设置在第二密封剂中。 垂直互连单元设置在第二密封剂中。 第三导电层形成在第二密封剂之上并且经由垂直互连单元电连接到积层互连结构。

    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
    18.
    发明授权
    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units 有权

    公开(公告)号：US10049964B2

    公开(公告)日：2018-08-14

    申请号：US14061244

    申请日：2013-10-23

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

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