公开(公告)号：US20160284751A1

公开(公告)日：2016-09-29

申请号：US15062020

申请日：2016-03-04

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Po-Han LEE ,  Jiun-Yen LAI

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  A61B5/1172 ,  B81B7/0067 ,  B81B7/007 ,  B81B2207/096 ,  G06K9/0004 ,  H01L21/76898 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0362 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/0579 ,  H01L2224/058 ,  H01L2224/11 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/0665

Abstract: This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to the first top surface, which comprises a sensing device near the first top surface, a plurality of conductive pads near the first top surface and adjacent to the sensing device; a plurality of through holes on the first top surface and each of the through holes exposing one of the conductive pads corresponding to with each other; a plurality of conductive structure formed on the first bottom surface; and a re-distribution layer (RDL) formed on the first bottom surface and the first through holes to respectively connect to each of the conductive pads and each of the conductive structures; a spacing layer, surrounding the sensing chip, formed on the sensing chip. The spacing layer has a second top surface, a second bottom surface and an opening through the second top surface and the second bottom surface, wherein the opening corresponds to the sensing device and the inner wall of the opening remains a desired distance d (d>0) with the sensing device; and a first adhesive layer sandwiched between the second bottom surface of the spacing layer and the first top surface of the sensing chip.

Abstract translation: 本发明提供了一种芯片尺度感测芯片封装，其包括具有第一顶表面和与第一顶表面相对的第一底表面的感测芯片，其包括靠近第一顶表面的感测装置，靠近第一顶表面的多个导电垫 第一顶表面并邻近感测装置; 所述第一顶表面上的多个通孔和每个所述通孔暴露彼此对应的所述导电焊盘之一; 形成在所述第一底面上的多个导电结构; 以及形成在所述第一底表面上的再分布层（RDL）和所述第一通孔，以分别连接到每个所述导电焊盘和每个所述导电结构; 围绕感测芯片的间隔层，形成在感测芯片上。 间隔层具有第二顶表面，第二底表面和穿过第二顶表面和第二底表面的开口，其中开口对应于感测装置，并且开口的内壁保持期望的距离d（d> 0）与感测装置; 以及夹在间隔层的第二底表面和感测芯片的第一顶表面之间的第一粘合剂层。

公开(公告)号：US20240304582A1

公开(公告)日：2024-09-12

申请号：US18431627

申请日：2024-02-02

Applicant: Xintec Inc.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU

IPC: H01L23/00 ,  H01L23/498 ,  H05K1/18

CPC classification number: H01L24/16 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H05K1/181 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/13155 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/16225 ,  H01L2924/1431

Abstract: A circuit substrate in a chip package is provided. The circuit substrate includes first and second insulating layers covering opposite first and second surfaces of the semiconductor substrate, respectively. The circuit substrate also includes first and second pads disposed in the first and second insulating layers, respectively, and laterally separated from an opening that extends from the first surface to the second surface of the semiconductor substrate. The circuit substrate further includes first and second under bump metallization (UBM) layers disposed on the first and second pads, respectively. The first UBM layer has a surface protruding above the first insulating layer, and the second UBM layer extends from the second pad onto the second insulating layer, and is partially recessed into the second insulating layer to form a concave surface.

公开(公告)号：US20190273175A1

公开(公告)日：2019-09-05

申请号：US16291637

申请日：2019-03-04

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Po-Han LEE ,  Chien-Min LIN ,  Yi-Rong HO

IPC: H01L31/12 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/18

Abstract: A chip package includes a chip, a sidewall structure that has a first light-shielding layer, a second light-shielding layer, and a cover. The chip has a light emitter and a light receiver that are located on a top surface of the chip. The sidewall structure is located on the top surface of the chip and has two aperture areas. The light emitter and the light receiver are respectively located in the two aperture areas. The sidewall structure surrounds the light emitter and the light receiver, and at least one surface of the sidewall structure has the first light-shielding layer. The second light-shielding layer is located between the chip and the sidewall structure. The cover is located on a surface of the sidewall structure facing away from the chip, and at least covers the light receiver and the sidewall structure that surrounds the light receiver.

公开(公告)号：US20170271276A1

公开(公告)日：2017-09-21

申请号：US15461334

申请日：2017-03-16

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Chia-Sheng LIN ,  Po-Han LEE ,  Wei-Luen SUEN

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/544 ,  H01L23/585 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/13024

Abstract: A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.

公开(公告)号：US20160181212A1

公开(公告)日：2016-06-23

申请号：US14958672

申请日：2015-12-03

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Po-Han LEE ,  Wei-Ming CHIEN

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/02 ,  B81C3/00 ,  H01L23/3114 ,  H01L23/315 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/29011 ,  H01L2224/29082 ,  H01L2224/29186 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2924/12041 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/0781 ,  H01L2924/0549 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0544 ,  H01L2924/0542 ,  H01L2924/0103 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/014 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/81

Abstract: A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. A dielectric layer is disposed on the first surface of the substrate and includes a conducting pad structure. A first opening penetrates the substrate and exposes a surface of the conducting pad structure. A second opening is communication with the first opening and penetrates the conducting pad structure. A redistribution layer is conformally disposed on a sidewall of the first opening and the surface of the conducting pad structure and is filled into the second opening. A method for forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括具有第一表面和与其相对的第二表面的基板。 电介质层设置在衬底的第一表面上并且包括导电焊盘结构。 第一开口穿透衬底并暴露导电垫结构的表面。 第二开口与第一开口连通并穿透导电垫结构。 再分配层保形地设置在第一开口的侧壁和导电垫结构的表面上，并被填充到第二开口中。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20150179831A1

公开(公告)日：2015-06-25

申请号：US14640307

申请日：2015-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L31/0232 ,  H01L31/028 ,  H01L31/0236 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/18

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

Abstract translation: 半导体结构包括硅衬底，保护层，电焊盘，隔离层，再分配层，导电层，钝化层和导电结构。 硅基板具有凹形区域，台阶结构，齿结构，第一表面和与第一表面相对的第二表面。 台阶结构和齿结构围绕凹区域。 台阶结构具有第一倾斜表面，第三表面和面对凹入区域并且依次连接的第二倾斜表面。 保护层位于硅衬底的第一表面上。 电焊盘位于保护层中，并通过凹面露出。 隔离层位于第一和第二倾斜表面，台阶结构的第二和第三表面以及齿结构上。

公开(公告)号：US20230369362A1

公开(公告)日：2023-11-16

申请号：US18312552

申请日：2023-05-04

Applicant: Xintec Inc.

Inventor： Po-Han LEE ,  Tsang Yu LIU ,  Chia-Ming CHENG ,  Kuei Wei CHEN ,  Jiun-Yen LAI

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14618 ,  H01L27/14687 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/29011 ,  H01L2224/94 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/33181 ,  H01L2224/33051 ,  H01L24/33

Abstract: A chip package includes a carrier board, a chip, a light transmissive sheet, a supporting element, and a molding material. The chip is located on the carrier board and has a sensing area. The light transmissive sheet is located above the supporting element and covers the sensing area of the chip. The supporting element is located between the light transmissive sheet and the chip, and surrounds the sensing area of the chip. The molding material is located on the carrier board and surrounds the chip and the light transmissive sheet. A top surface of the molding material is lower than a top surface of the light transmissive sheet.

公开(公告)号：US20180358398A1

公开(公告)日：2018-12-13

申请号：US15996841

申请日：2018-06-04

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Po-Han LEE

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14636 ,  H01L24/02 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14632 ,  H01L27/14678 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/13024

Abstract: A chip package includes a chip, an isolation layer, a redistribution layer, a passivation layer, and an encapsulation layer. The chip has a sensor, a conductive pad, a through hole, a top surface, and a bottom surface that is opposite the top surface. The sensor and the conductive pad are located on the top surface, and the conductive pad is in the through hole. The isolation layer is located on the bottom surface of the chip and a sidewall that surrounds the through hole. The redistribution layer is located on the isolation layer, and is in electrical contact with the conductive pad. The passivation layer is located on the isolation layer and the redistribution layer. The encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad, and has a flat surface facing away from the chip.

公开(公告)号：US20180337142A1

公开(公告)日：2018-11-22

申请号：US15980577

申请日：2018-05-15

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Po-Han LEE ,  Wei-Chung YANG ,  Kuan-Jung WU ,  Shu-Ming CHANG

IPC: H01L23/00 ,  H01L25/16 ,  H01L27/146 ,  H01L21/56 ,  H01L23/31 ,  H01L23/04

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/561 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L25/167 ,  H01L27/14643 ,  H01L2224/02373

Abstract: A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.

公开(公告)号：US20170148844A1

公开(公告)日：2017-05-25

申请号：US15358852

申请日：2016-11-22

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Hsiao-Lan YEH ,  Chia-Sheng LIN ,  Yi-Ming CHANG ,  Po-Han LEE ,  Hui-Hsien WU ,  Jyun-Liang WU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chien-Min LIN

IPC: H01L27/146 ,  H01L21/48 ,  H01L21/67 ,  H01L23/18

CPC classification number: H01L27/14698 ,  H01L21/4803 ,  H01L21/67017 ,  H01L21/67132 ,  H01L23/18 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.