公开(公告)号：US09779804B2

公开(公告)日：2017-10-03

申请号：US15345552

申请日：2016-11-08

Applicant: Conversant Intellectual Property Management Inc.

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US09762120B2

公开(公告)日：2017-09-12

申请号：US15174050

申请日：2016-06-06

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Peter Vlasenko ,  Huy Tuong Mai

IPC: H03L7/06 ,  H02M3/07 ,  H02M1/34 ,  H03K5/08 ,  H03L7/089 ,  G05F3/02 ,  G05F1/625

CPC classification number: H02M3/07 ,  G05F1/625 ,  G05F3/02 ,  H02M1/34 ,  H02M3/073 ,  H03K5/086 ,  H03L7/0895

Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

公开(公告)号：US09704580B2

公开(公告)日：2017-07-11

申请号：US13830135

申请日：2013-03-14

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hyoung Seub Rhie

IPC: G11C16/06 ,  G11C16/14

CPC classification number: G11C16/06 ,  G11C16/14

Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

公开(公告)号：US09595534B2

公开(公告)日：2017-03-14

申请号：US14938259

申请日：2015-11-11

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub Rhie

IPC: G11C16/10 ,  H01L27/115 ,  G11C16/04 ,  G11C16/14

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.

Abstract translation: 包括阱和U形闪存单元串的闪存器件，U形闪存单元串直接构建在与阱相邻的衬底上。 U形闪存单元串包括平行于衬底的表面的一个部分，包括无连接底部传输晶体管，以及垂直于衬底表面的两个部分，其包括在电池串的第一顶部的串选择晶体管， 在单元串的第二顶部的接地选择晶体管，串选择晶体管漏极和接地选择晶体管源。

公开(公告)号：US09490014B2

公开(公告)日：2016-11-08

申请号：US14964958

申请日：2015-12-10

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Jin-Ki Kim ,  Hong Beom Pyeon

IPC: G11C16/00 ,  G11C16/08 ,  G06F13/42 ,  G11C5/06 ,  G11C7/10 ,  G11C8/10 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract translation: 公开了一种用于控制半导体存储器中的多个串行数据链路接口和多个存储体之间的数据传输的装置，系统和计算机实现的方法。 在一个示例中，公开了具有多个链路和存储体的闪存器件，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

公开(公告)号：US20160322095A1

公开(公告)日：2016-11-03

申请号：US15054873

申请日：2016-02-26

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki KIM ,  HakJune OH

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

公开(公告)号：US20160172027A1

公开(公告)日：2016-06-16

申请号：US14571949

申请日：2014-12-16

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Ehsan Tahmasebian ,  Hyoung Seub Rhie ,  Peter Gillingham

IPC: G11C13/00 ,  H01L51/00 ,  H01L51/10

CPC classification number: G11C13/0016 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C2013/0054 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/72 ,  G11C2213/73 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L51/0595

Abstract: A integrated circuit device with a polymer memory array includes active circuits formed in lower layers of a multi-level interconnect structure and a semiconductor substrate and also includes an array of polymer memory cells formed in an upper interconnect level having a plurality of cell node electrodes and source line electrodes for the polymer memory array, each polymer memory cell including a passive layer having at least one conductivity-facilitating compound that is formed on top and sidewall surfaces of a source line electrode, and an active layer having an impedance state that can change that is formed on top and sidewall surfaces of an adjacent cell node electrode with sufficient thickness to make direct physical contact with the passive layer.

Abstract translation: 具有聚合物存储器阵列的集成电路器件包括形成在多层互连结构的下层中的有源电路和半导体衬底，并且还包括形成在具有多个单元节点电极的上部互连电平中的聚合物存储器单元的阵列， 用于聚合物存储器阵列的源极线电极，每个聚合物存储单元包括具有形成在源极线电极的顶壁和侧壁表面上的至少一种导电性促进化合物的钝化层，以及具有可改变的阻抗状态的有源层 其形成在相邻电池节点电极的顶壁和侧壁表面上，具有足够的厚度以与被动层直接物理接触。

公开(公告)号：US09350349B2

公开(公告)日：2016-05-24

申请号：US14480143

申请日：2014-09-08

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Barry A. Hoberman ,  Daniel L. Hillman ,  William G. Walker ,  John M. Callahan ,  Michael A. Zampaglione ,  Andrew Cole

IPC: H03K19/17 ,  H03K19/003 ,  G11C5/14 ,  H03K3/356 ,  H03K17/10 ,  H03K19/00 ,  H03K5/14

CPC classification number: H03K19/0016 ,  G11C5/14 ,  G11C5/144 ,  G11C5/148 ,  H02M3/07 ,  H03K3/0372 ,  H03K3/356086 ,  H03K3/356113 ,  H03K5/14 ,  H03K17/102 ,  H03K19/00315

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

公开(公告)号：US09300291B2

公开(公告)日：2016-03-29

申请号：US14499275

申请日：2014-09-29

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Bruce Millar

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00 ,  G11C5/06 ,  G11C7/02 ,  G11C7/10 ,  G11C11/4093 ,  H03H7/38 ,  H04L25/02 ,  H03H17/00

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4093 ,  G11C2207/2254 ,  H03H7/38 ,  H03H17/0045 ,  H04L25/0278 ,  H04L25/028

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

Abstract translation: 提供了执行片外驱动（OCD）和片上终端（ODT）的系统和方法。 由晶体管组成的公共上拉网络和由晶体管组成的公共下拉网络被采用来实现这两个功能。 在驱动模式下，上拉网络被配置为当要产生“开”输出时产生校准的驱动阻抗，并且当“关”输出为“关”时，上拉网络被配置为产生校准的驱动阻抗 生成。 在终端模式中，上拉网络和下拉网络被配置为分别产生校准的上拉电阻和下拉电阻，使得它们一起形成分离终端。

公开(公告)号：US09237518B2

公开(公告)日：2016-01-12

申请号：US14551732

申请日：2014-11-24

Applicant: Conversant Intellectual Property Management Incorporated

Inventor： Nima Ahmadvand ,  Xuejun Lu ,  Hanwu Hu ,  Mouhamadou Lamine Sylla

IPC: H04W52/02 ,  H04W36/00 ,  H04W84/12

CPC classification number: H04W52/0206 ,  H04W36/0055 ,  H04W52/02 ,  H04W52/0219 ,  H04W84/12 ,  Y02D70/00 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/146 ,  Y02D70/22

Abstract: Power saving in wireless networks is disclosed. A wireless network entity that includes a module to enable a reduction in power consumption in that wireless network entity is also disclosed. The module is configured to determine that a selected wireless station of one or more wireless stations associated with the wireless network entity in a same wireless network will transmit system control information (including synchronization information and service identification information) that is normally transmitted by the wireless network entity.

Abstract translation: 公开了无线网络中的省电。 还公开了一种包括能够降低该无线网络实体中的功率消耗的模块的无线网络实体。 该模块被配置为确定与相同无线网络中的无线网络实体相关联的一个或多个无线站的所选无线站将发送正常由无线网络发送的系统控制信息（包括同步信息和服务标识信息） 实体。