公开(公告)号：US07897509B2

公开(公告)日：2011-03-01

申请号：US12823913

申请日：2010-06-25

Applicant: Naotaka Tanaka ,  Kenji Kanemitsu ,  Takafumi Kikuchi ,  Takashi Akazawa

Inventor： Naotaka Tanaka ,  Kenji Kanemitsu ,  Takafumi Kikuchi ,  Takashi Akazawa

IPC: H01L21/4763

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/90 ,  H01L2224/0554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.

Abstract translation: 一种半导体晶片，包括：在形成晶片的通孔电极的位置处形成的管状沟槽; 绝缘构件，其被埋置在所述沟槽内部和所述沟槽的上表面上; 形成在所述绝缘构件的上表面上的栅电极膜和金属膜; 形成在金属膜的上表面上的多层柱状布线孔; 以及通过多层柱状布线通孔与金属膜电连接形成的外部连接电极。 以这种方式，在薄晶片和设备开发之后，不需要具有干法蚀刻的新工艺来形成通孔电极。 此外，引入特定设计可以形成通孔电极，同时显着降低了各个工艺的难度。

公开(公告)号：US07786585B2

公开(公告)日：2010-08-31

申请号：US12188591

申请日：2008-08-08

Applicant: Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

Inventor： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Abstract translation: 在具有多层埋地布线的半导体集成电路装置中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

公开(公告)号：US07782025B2

公开(公告)日：2010-08-24

申请号：US12349106

申请日：2009-01-06

Applicant: Takayuki Hashimoto ,  Nobuyoshi Matsuura ,  Masaki Shiraishi ,  Yukihiro Satou ,  Tetsuya Kawashima

Inventor： Takayuki Hashimoto ,  Nobuyoshi Matsuura ,  Masaki Shiraishi ,  Yukihiro Satou ,  Tetsuya Kawashima

IPC: G05F1/613

CPC classification number: H01L25/16 ,  H01L25/074 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/4903 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.

Abstract translation: 提供能够减小电感的半导体器件。 在其中将整流MOSFET，换向MOSFET和驱动这些MOSFET的驱动IC安装在一个封装上的半导体器件中，整流MOSFET，金属板和换向MOSFET被层压。 主电路的电流从封装的后表面流向其前表面。 金属板通过封装中的布线连接到输出端子。 引线键合用于连接驱动IC，整流MOSFET和换向MOSFET，所有端子都放置在同一平面上。 因此，电感变小，电源损耗和尖峰电压也降低。

公开(公告)号：US08685866B2

公开(公告)日：2014-04-01

申请号：US12822317

申请日：2010-06-24

Applicant: Sadayoshi Horii ,  Atsushi Sano ,  Masahito Kitamura ,  Yoshitake Kato

Inventor： Sadayoshi Horii ,  Atsushi Sano ,  Masahito Kitamura ,  Yoshitake Kato

IPC: H01L21/31

CPC classification number: H01L21/3141 ,  C23C16/40 ,  C23C16/403 ,  C23C16/405 ,  C23C16/4412 ,  C23C16/45531 ,  C23C16/45561 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228

Abstract: A method of manufacturing a semiconductor device including alternately repeating a process of forming a first metal oxide film including a first metal element and a process of forming a second metal oxide film including a second metal element on a substrate accommodated in a processing chamber, so as to form a third metal oxide film including the first and second metal elements with a predetermined composition ratio on the substrate. One of the first and second metal elements of the third metal oxide film has a concentration higher than a concentration of the other, and one of the first and second metal oxide films including the higher-concentration metal element is formed in a chemical vapor deposition (CVD) mode or an atomic layer deposition (ALD) saturation mode, and the other of the first and second metal oxide films is formed in an ALD unsaturation mode.

Abstract translation: 一种制造半导体器件的方法，包括交替地重复形成包括第一金属元素的第一金属氧化物膜的工艺和在容纳在处理室中的基板上形成包括第二金属元素的第二金属氧化物膜的工艺，以便 在衬底上形成具有预定组成比的第一和第二金属元素的第三金属氧化物膜。 第三金属氧化物膜的第一和第二金属元素中的一个具有比另一个的浓度高的浓度，并且包括高浓度金属元素的第一和第二金属氧化物膜中的一个在化学气相沉积中形成 CVD）模式或原子层沉积（ALD）饱和模式，并且第一和第二金属氧化物膜中的另一个以ALD不饱和模式形成。

公开(公告)号：US07791131B2

公开(公告)日：2010-09-07

申请号：US11645577

申请日：2006-12-27

Applicant: Tomoyuki Miyake ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Makoto Hatori

Inventor： Tomoyuki Miyake ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Makoto Hatori

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/62 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66659 ,  H01L21/823425 ,  H01L23/3677 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/7835 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n+ type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n− type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.

Abstract translation: 为了减小尺寸并提高具有由硅功率MOSFET组成的放大器元件的RF功率模块的功率附加效率，传统上处于折衷关系的导通电阻和反馈电容通过形成结构 存在于功率MOSFET的栅极电极和n +型漏极区域之间的偏移漏极区域，成为双偏移漏极区域。 更具体地说，这是通过将最接近栅电极的n型偏移漏极区域的杂质浓度调整为相对较低而调整n型偏移漏极区域的杂质浓度来实现的，该杂质浓度远离 栅电极，要比较高。

公开(公告)号：US20110177663A1

公开(公告)日：2011-07-21

申请号：US13076833

申请日：2011-03-31

Applicant: TSUYOSHI KACHI

Inventor： TSUYOSHI KACHI

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: Generally, a power MOSFET mainly includes an active region occupying most of an internal region (a region where a gate electrode made of polysilicon or the like is integrated), and a surrounding gate contact region (where the gate electrode made of polysilicon or the like is derived outside a source metal covered region to make contact with a gate metal) (see FIG. 65 in a comparative example). Since the gate electrode made of polysilicon or the like has a stepped portion existing between both regions, a focus margin maybe reduced in a lithography step, including exposure or the like, for formation of a contact hole for a source or for a gate. The invention of the present application provides a semiconductor device having a trench gate type power MISFET with a gate electrode protruding from an upper surface of a semiconductor substrate, in which respective main upper surfaces of the gate electrode in an active region and a gate contact region are substantially at the same height.

Abstract translation: 通常，功率MOSFET主要包括占据大部分内部区域（由多晶硅等形成的栅电极的区域）的有源区域和周围的栅极接触区域（其中由多晶硅等构成的栅极电极 衍生在源极金属覆盖区域外部以与栅极金属接触）（参见比较例中的图65）。 由于由多晶硅等制成的栅电极具有存在于两个区域之间的阶梯部分，所以在用于形成用于源极或栅极的接触孔的曝光等的光刻步骤中可能减小焦距。 本申请的发明提供了一种半导体器件，其具有沟槽栅型功率MISFET，栅极电极从半导体衬底的上表面突出，其中有源区中的栅电极的主要上表面和栅极接触区域 基本上处于相同的高度。

公开(公告)号：USRE41722E1

公开(公告)日：2010-09-21

申请号：US10105236

申请日：2002-03-26

Applicant: Atsushi Nakamura ,  Kunihiko Nishi

Inventor： Atsushi Nakamura ,  Kunihiko Nishi

IPC: H01L23/49 ,  H01L23/13 ,  H01L23/48 ,  H01L23/31 ,  H01L23/12 ,  H01L23/498 ,  H01L23/28

CPC classification number: H01L24/49 ,  B29C45/0046 ,  B29C45/14655 ,  B29C45/14836 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48221 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85206 ,  H01L2224/85207 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/0695 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.

公开(公告)号：US07785986B2

公开(公告)日：2010-08-31

申请号：US12400892

申请日：2009-03-10

Applicant: Yoshihisa Matsubara ,  Hiromichi Suzuki ,  Wahei Kitamura ,  Kosho Akiyama ,  Seiji Kato

Inventor： Yoshihisa Matsubara ,  Hiromichi Suzuki ,  Wahei Kitamura ,  Kosho Akiyama ,  Seiji Kato

IPC: H01L21/30 ,  H01L23/34

CPC classification number: H01L21/67333 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.

Abstract translation: 为了防止半导体芯片在运输期间粘附到托盘，采用以下状态传输半导体芯片的方法。 当具有多个具有用于在其主表面上容纳半导体芯片的凹入截面的容纳部分的托盘被堆叠成多级时，半导体芯片被容纳在形成在主表面上的容纳部分所形成的空间中 下级托盘和形成在上级托盘的后表面上的相应的容纳部分。 这里，在形成在上层托盘的后表面上的容纳部分的底表面上，以散射方式布置具有防止突起与半导体芯片接触的高度的隔离突起。 以这种方式，可以防止半导体芯片粘附到上层托盘的后表面。

公开(公告)号：US07745921B2

公开(公告)日：2010-06-29

申请号：US12264970

申请日：2008-11-05

Applicant: Kazuhiko Hiranuma ,  Hiroshi Kuroda ,  Yoshiyuki Abe

Inventor： Kazuhiko Hiranuma ,  Hiroshi Kuroda ,  Yoshiyuki Abe

IPC: H01L23/02

CPC classification number: H01L27/14618 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/14634 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes semiconductor chips differing in withstand voltage or in noise immunity, such as a multi-chip module. The semiconductor device includes first and second semiconductor chips mounted over a package substrate which has bonding pads arranged along the edges. The first semiconductor chip includes bonding pads for analog signals, and the second semiconductor chip includes bonding pads for high-voltage signals. The edges along which the bonding pads for analog signals are arranged and the edges along which the bonding pads for high-voltage signals are arranged are disposed along mutually different edges of the package substrate. Adjoining of electrodes or wirings for high voltage signals and those for analog signals over the package substrate can be easily avoided, and SI deterioration can be thereby restrained.

Abstract translation: 半导体器件包括不同于耐电压或抗噪声的诸如多芯片模块的半导体芯片。 半导体器件包括安装在封装衬底上的第一和第二半导体芯片，该封装衬底具有沿边缘布置的焊盘。 第一半导体芯片包括用于模拟信号的接合焊盘，第二半导体芯片包括用于高电压信号的焊盘。 布置用于模拟信号的接合焊盘的边缘以及布置有用于高电压信号的接合焊盘的边缘沿着封装衬底的相互不同的边缘设置。 可以容易地避免用于高电压信号的电极或布线与封装基板上的模拟信号的连接，从而可以抑制SI劣化。

公开(公告)号：US735484A

公开(公告)日：1903-08-04

申请号：US1902127634

申请日：1902-10-17

Applicant: EVENS EDWARD LUSCOMBE

Inventor： EVENS EDWARD LUSCOMBE

CPC classification number: A62B1/02 ,  E04G3/34