公开(公告)号：US20240110262A1

公开(公告)日：2024-04-04

申请号：US18275599

申请日：2022-01-31

申请人： NIPPON MICROMETAL CORPORATION ,  NIPPON STEEL Chemical & Material Co., Ltd.

发明人： Tomohiro UNO ,  Yuya SUTO ,  Tetsuya OYAMADA ,  Daizo ODA ,  Yuto KURIHARA ,  Motoki ETO

IPC分类号： C22C21/14 ,  C22C1/02 ,  C22C21/00 ,  C22C21/02 ,  C22C21/08 ,  C22C21/16 ,  C22F1/043 ,  C22F1/047 ,  C22F1/057 ,  H01L23/00

CPC分类号： C22C21/14 ,  C22C1/026 ,  C22C21/00 ,  C22C21/02 ,  C22C21/08 ,  C22C21/16 ,  C22F1/043 ,  C22F1/047 ,  C22F1/057 ,  H01L24/45 ,  H01L2224/45124

摘要： There is provided an Al wiring material which can achieve sufficient bond reliability of bonded parts in a high-temperature environment at the time when a semiconductor device operates. The Al wiring material containing one or more of Pd and Pt so as to satisfy


3≤x1a≤90 or 10≤x1b≤250, and



3≤(x1a+x1b)≤300,



where x1a and x1b are respectively a content of Pd [mass ppm] and a content of Pt [mass ppm],
with the balance comprising Al, and
an average crystal grain diameter on a cross-section perpendicular to a longitudinal direction of the Al wiring material is 3 to 35 μm.

公开(公告)号：US20240106342A1

公开(公告)日：2024-03-28

申请号：US18477243

申请日：2023-09-28

申请人： ZF Friedrichshafen AG

发明人： Zhiwu Hu ,  Tianyuan Dong ,  Zhao Li

IPC分类号： H02M7/00 ,  H01L23/00 ,  H01L23/498 ,  H01L25/07 ,  H02M7/5387

CPC分类号： H02M7/003 ,  H01L23/49811 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H02M7/5387 ,  H01L2224/37147 ,  H01L2224/40137 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/73271

摘要： A half-bridge power device includes a module substrate, the upper surface of which includes a first half-bridge area, a second half-bridge area, a first half-bridge lead-out area, and a second half-bridge lead-out area, which are separate, the first and second half-bridge lead-out areas being located at the ends of the module substrate. The first and second half-bridge power chips are connected to the first half-bridge area and the second half-bridge area, respectively. The first, second, and third power connector terminals are connected to the first and second half-bridge areas, and the first and second half-bridge power chips to form a power loop.

公开(公告)号：US20240105667A1

公开(公告)日：2024-03-28

申请号：US18263000

申请日：2022-01-25

申请人： TANAKA DENSHI KOGYO K.K. ,  MITSUBISHI ELECTRIC CORPORATION

发明人： Shuichi MITOMA ,  Tsukasa ICHIKAWA ,  Tsuyoshi URAJI ,  Tatsunori YANAGIMOTO ,  Dai NAKAJIMA

IPC分类号： H01L23/00 ,  C22C21/00 ,  C22F1/00 ,  C22F1/04

CPC分类号： H01L24/45 ,  C22C21/00 ,  C22F1/002 ,  C22F1/04 ,  H01L24/05 ,  H01L24/48 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05138 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05663 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45105 ,  H01L2224/45124 ,  H01L2224/45138 ,  H01L2224/4516 ,  H01L2224/45172 ,  H01L2224/4801 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/0135 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13091

摘要： An aluminum wire with which, at the time of bonding a bonding wire for a power semiconductor, the wire is not detached from a wedge tool, and a long life is achieved in a power cycle test. The aluminum wire is made of an aluminum alloy having an aluminum purity of 99 mass % or more and contains, relative to a total amount of all elements of the aluminum alloy, a total of 0.01 mass % or more and 1 mass % or less of iron and silicon. In a lateral cross-section in a direction perpendicular to a wire axis of the aluminum wire, an orientation index of is 1 or more, an orientation index of is 1 or less, and an area ratio of precipitated particles is in a range of 0.02% or more to 2% or less.

公开(公告)号：US11923258B2

公开(公告)日：2024-03-05

申请号：US17469480

申请日：2021-09-08

申请人： Texas Instruments Incorporated

发明人： William Robert Morrison ,  Bradley Morgan Haskett

IPC分类号： H01L23/13 ,  H01L23/00 ,  H01L23/08 ,  H01L23/31

CPC分类号： H01L23/13 ,  H01L23/08 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48227

摘要： An example includes: a substrate having a first package surface, having a second package surface opposite the first package surface, and having a die cavity with a depth extending into the first package surface; a semiconductor die having bond pads on a first die surface and having a second die surface opposite the first die surface, the semiconductor die having a die thickness, the second die surface of the semiconductor die mounted in the die cavity; a cover over a portion of the first die surface; conductors coupling the bond pads of the semiconductor die to bond fingers on the first package surface of the substrate; and dielectric material over the conductors, the bond fingers, the bond pads, at least a portion of the first semiconductor die and at least a portion of the cover, wherein the dielectric material extends above the first package surface of the substrate.

公开(公告)号：US11901210B2

公开(公告)日：2024-02-13

申请号：US17880653

申请日：2022-08-04

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H10B20/20

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1579 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/30105 ,  H10B12/05 ,  H10B20/20

摘要： A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.

公开(公告)号：US11830757B1

公开(公告)日：2023-11-28

申请号：US18228675

申请日：2023-08-01

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H10B20/20

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1579 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/30105 ,  H10B12/05 ,  H10B20/20

摘要： A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the at least one of the second transistors transistor channel includes non-silicon atoms, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

公开(公告)号：US20230369410A1

公开(公告)日：2023-11-16

申请号：US18142050

申请日：2023-05-02

申请人： Infineon Technologies Austria AG

发明人： Elias Pree ,  Peter Lagger

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L23/00 ,  H01L29/06

CPC分类号： H01L29/1095 ,  H01L29/7813 ,  H01L29/66734 ,  H01L24/05 ,  H01L24/48 ,  H01L24/06 ,  H01L29/0696 ,  H01L24/45 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/45144 ,  H01L2224/45124 ,  H01L2224/48175 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L29/407

摘要： A transistor device includes a semiconductor substrate having a first major surface and transistor cells formed therein. Each transistor cell includes a drift region of a first conductivity type, a body region of an opposing second conductivity type arranged on the drift region, a source region of the first conductivity type arranged on the body region, a columnar field plate trench extending into the first major surface and including a field plate, and a gate trench structure extending into the first major surface and including a gate electrode. A first metallization structure on the first major surface provides a first contact pad for wire bonding. At least one of depth and doping level of the body region is locally increased within the transistor cells located within one or more first areas of the first major surface. One or more of the first areas are located underneath the first contact pad.

公开(公告)号：US11804396B2

公开(公告)日：2023-10-31

申请号：US18200387

申请日：2023-05-22

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H10B20/20

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1579 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/30105 ,  H10B12/05 ,  H10B20/20

摘要： A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing processing steps to form first memory cells within the second level and form second memory cells within the third level, where the first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and then at performing at least one deposition step which deposits gate electrodes for both the second and the third transistors, and forming at least four independent memory arrays.

公开(公告)号：US11784201B2

公开(公告)日：2023-10-10

申请号：US17186164

申请日：2021-02-26

申请人： CANON KABUSHIKI KAISHA

发明人： Kazuya Notsu ,  Ayako Furesawa

IPC分类号： H01L27/146 ,  H01L23/498 ,  H01L23/055 ,  H01L23/49 ,  H01L23/00

CPC分类号： H01L27/14618 ,  H01L23/055 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L23/49 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/1318 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/16227 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81201

摘要： A package comprising a base is provided. An electrode and a concave portion are arranged on a first surface of the package. The base comprises a second surface on a side opposite to the first surface and a third surface. The first surface is positioned between the second and third surfaces. The electrode comprises an electrode upper surface and an electrode side surface. The concave portion comprises a concave side surface and a bottom surface positioned closer to the second surface than the concave side surface. The electrode upper surface is arranged at a position further away from the virtual plane than the bottom surface. The electrode side surface is continuous with the concave side surface. The concave portion further comprises a second side surface which faces the concave side surface and is continuous with the third surface.

公开(公告)号：US20230282611A1

公开(公告)日：2023-09-07

申请号：US18159272

申请日：2023-01-25

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hiroki TAKAHASHI ,  Tsunehiro NAKAJIMA ,  Takashi SAITO

IPC分类号： H01L23/00 ,  H01L25/07 ,  H01L25/00

CPC分类号： H01L24/83 ,  H01L24/95 ,  H01L24/32 ,  H01L24/29 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/95053 ,  H01L2224/83054 ,  H01L2224/83201 ,  H01L2224/8384 ,  H01L2224/83815 ,  H01L2224/83948 ,  H01L2224/83455 ,  H01L2924/0132 ,  H01L2224/83463 ,  H01L2924/01005 ,  H01L2224/83439 ,  H01L2224/83395 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2924/13055 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13091 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/73263 ,  H01L2224/40225 ,  H01L2224/73265 ,  H01L2224/73221 ,  H01L24/48 ,  H01L2224/48225 ,  H01L2224/48106 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45124 ,  H01L24/37 ,  H01L2224/37147 ,  H01L2224/37655 ,  H01L2224/37638

摘要： When a semiconductor unit is heated, a heater having a flat heating surface is used for performing heating in a state in which a lower surface of an insulated circuit board is placed on the heating surface. When the semiconductor unit is cooled, a cooler having a cooling surface including a pair of support portions is used for performing cooling in which a lower surface of a pair of outer regions of the insulated circuit board are respectively placed to be contact with the pair of support portions, and in which a central region between the pair of outer regions of the insulated circuit board is pressed downward so as to be downward convex.