公开(公告)号：US20080035362A1

公开(公告)日：2008-02-14

申请号：US11923413

申请日：2007-10-24

Applicant: Young Kwark ,  Christian Schuster

Inventor： Young Kwark ,  Christian Schuster

IPC: H05K9/00 ,  B23K31/02

CPC classification number: H01L24/46 ,  H01L23/66 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/73 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2224/43 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49174 ,  H01L2224/8502 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/1903 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/0219 ,  H05K1/0243 ,  H05K2201/0792 ,  H05K2201/09236 ,  H05K2201/1028 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method (and structure) of making an electronic interconnection, includes, for a signal line to be interconnected, using a plurality of bonding wires configured to provide a controlled impedance effect.

Abstract translation: 制造电子互连的方法（和结构）包括用于要互连的信号线，使用被配置为提供受控阻抗效应的多个接合线。

公开(公告)号：US07279771B2

公开(公告)日：2007-10-09

申请号：US11090029

申请日：2005-03-28

Applicant: Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi ,  Toshio Gomyo ,  Yukiharu Takeuchi

Inventor： Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi ,  Toshio Gomyo ,  Yukiharu Takeuchi

IPC: H01L29/00 ,  H05K1/14 ,  H05K1/03

CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611

Abstract: In a capacitor-mounted wiring board, a plurality of wiring layers each patterned in a required shape are stacked with insulating layers interposed therebetween and are connected to each other via conductors formed to pierce the insulating layers in the direction of thickness. A decoupling capacitor is electrically connected to a wiring layer used as a power supply line or a ground line in the vicinity of the wiring layer, and mounted such that, when a current is passed through the capacitor, the direction of the current is reversed to that of the current flowing through the relevant wiring layer.

Abstract translation: 在电容器安装的布线板中，以所需形状图案化的多个布线层被叠置在其间插入绝缘层，并且通过形成为在厚度方向上刺穿绝缘层的导体彼此连接。 去耦电容器电连接到用作布线层附近的电源线或接地线的布线层，并且安装成使得当电流通过电容器时，电流的方向被反转到 流过相关布线层的电流。

公开(公告)号：US07274837B2

公开(公告)日：2007-09-25

申请号：US11022793

申请日：2004-12-28

Applicant: Tomokazu Tanaka ,  Tadashi Hatano ,  Hiroo Matsue ,  Cleitus Antony

Inventor： Tomokazu Tanaka ,  Tadashi Hatano ,  Hiroo Matsue ,  Cleitus Antony

IPC: G02B6/12

CPC classification number: H05K1/0243 ,  G02B6/4201 ,  G02B6/4245 ,  G02B6/4279 ,  G02B6/428 ,  G02B6/4281 ,  G02B6/4283 ,  H05K1/162 ,  H05K1/18 ,  H05K3/306 ,  H05K2201/0715 ,  H05K2201/0792 ,  H05K2201/10106 ,  H05K2201/10121 ,  H05K2201/2036

Abstract: An optical transmitter in which a microstripline is formed by a signal wiring pattern and a GND conductor pattern on a circuit board (including a flexible board), and a signal lead of a light emitting element module is mounted in a signal lead mounting hole connected with said signal wiring pattern so as to be connected with said signal wiring pattern, wherein a pattern adapted to add capacitance between a stem of said light emitting element module and said signal wiring pattern is provided on said signal wiring pattern on said circuit board, and wherein the pattern adapted to add capacitance has a size corresponding to ±50% of a capacitance C≈L/Zo2, where Zo is signal line impedance, and L is the signal lead inductance.

Abstract translation: 一种光发射机，其中微带线由电路板（包括柔性板）上的信号布线图案和GND导体图案形成，并且发光元件模块的信号引线安装在与 所述信号布线图形与所述信号布线图形连接，其中在所述电路板上的所述信号布线图案上设置适于在所述发光元件模块的杆和所述信号布线图案之间增加电容的图案，其中 适于添加电容的图案的尺寸对应于电容C≈L/ Zo 2的±50％，其中Zo是信号线阻抗，L是信号引线电感。

公开(公告)号：US20070183131A1

公开(公告)日：2007-08-09

申请号：US11451292

申请日：2006-06-12

Applicant: Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

Inventor： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC: H04B3/28 ,  H05K9/00

CPC classification number: H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Abstract translation: 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。

公开(公告)号：US20070139063A1

公开(公告)日：2007-06-21

申请号：US11313333

申请日：2005-12-21

Applicant: Xingjian Cai ,  Xiao-Ming Gao ,  Qing-Iun Chen

Inventor： Xingjian Cai ,  Xiao-Ming Gao ,  Qing-Iun Chen

IPC: G01R31/02

CPC classification number: H05K7/1458 ,  H05K1/0215 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/025 ,  H05K1/14 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/0792 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10196

Abstract: An apparatus comprising a printed circuit board having a front side and a back side, and having therein a plurality of conductive layers, each conductive layer including one or more signal channels; a stub extending from the front side to the back side, the stub being electrically coupled to at least one signal channel; and an impedance matching terminal electrically coupled to the stub and to a ground. A process comprising providing a printed circuit board including a front side and a back side, and having therein a plurality of conductive layers, each conductive layer including one or more signal channels, and a stub extending from the front side to the back side, the stub being electrically coupled to at least one signal channel and being designed to receive a signal from a component attached to the printed circuit board; and coupling an impedance matching terminal to the stub and to a ground.

Abstract translation: 一种装置，包括具有前侧和后侧的印刷电路板，并且其中具有多个导电层，每个导电层包括一个或多个信号通道; 从前侧延伸到后侧的短截线，短截线电耦合到至少一个信号通道; 以及电阻耦合到短截线和接地的阻抗匹配端子。 一种包括提供包括前侧和后侧的印刷电路板的工艺，其中包括多个导电层，每个导电层包括一个或多个信号通道，以及从前侧向后侧延伸的短截线 短截线被电耦合到至少一个信号通道并且被设计成从附接到印刷电路板的部件接收信号; 并将阻抗匹配端子耦合到短截线和接地。

公开(公告)号：US20060185890A1

公开(公告)日：2006-08-24

申请号：US10906466

申请日：2005-02-22

Applicant: Thomas Robinson

Inventor： Thomas Robinson

IPC: H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0237 ,  H05K1/024 ,  H05K1/115 ,  H05K1/18 ,  H05K2201/0792 ,  H05K2201/09063

Abstract: A wiring board (10) having reduced electromagnetic coupling between electronic devices includes a base board (12) that is adaptable to receive at least one electronic component (14) mounted on the base board (12). At least one hole or void (16) is formed in the base board (12). The hole (16) is separated from the selected electronic component (14) to be isolated against undesired electromagnetic radiation by a portion (18) of the base board (12).

Abstract translation: 在电子设备之间具有减小的电磁耦合的布线板（10）包括适于容纳安装在基板（12）上的至少一个电子部件（14）的基板（12）。 至少一个孔或空隙（16）形成在基板（12）中。 所述孔（16）与所选择的电子部件（14）分离，以被所述基板（12）的一部分（18）与所述电磁辐射隔离。

公开(公告)号：US20060170072A1

公开(公告)日：2006-08-03

申请号：US11340682

申请日：2006-01-27

Applicant: Yasutaka Nakashiba

Inventor： Yasutaka Nakashiba

IPC: H01L29/00

CPC classification number: H01L23/5227 ,  H01F17/0013 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0233 ,  H05K1/111 ,  H05K1/165 ,  H05K2201/0792 ,  H05K2201/09809 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device, includes: a semiconductor substrate; a multilayered interconnect structure formed on the semiconductor substrate; a terminal for flip-chip packaging arranged on the surface of the multilayered interconnect structure; and a spiral inductor formed to enclose the terminal for flip-chip packaging, in a plan view, which is not electrically connected with the spiral inductor. The spiral inductor may be provided for peaking by which the gain reduction caused in a high frequency is compensated.

公开(公告)号：US20060044895A1

公开(公告)日：2006-03-02

申请号：US10924629

申请日：2004-08-24

Applicant: Abeye Teshome ,  Lan Zhang

Inventor： Abeye Teshome ,  Lan Zhang

IPC: G11C29/00

CPC classification number: H05K1/0216 ,  H05K1/0263 ,  H05K1/112 ,  H05K1/162 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/10734 ,  Y10T29/49128 ,  Y10T29/49169

Abstract: Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.

Abstract translation: 通过电路板提供给信息处理系统电子元件的功率具有通过配置与电子元件的连接以补偿寄生电容的组件封装电感寄生效应。 例如，将处理器连接到电路板的电源和接地平面的电源和接地通孔被对准以产生期望的寄生电容，其减少与信号补偿，功率输送和高速解耦有关的寄生电感的影响。 期望的分布电容通过改变与功率通孔的等效线电荷相关联的半径，与电源和接地通孔之间的线路电荷相关联的距离以及通孔筒长度来建模。

公开(公告)号：US20060018104A1

公开(公告)日：2006-01-26

申请号：US11080672

申请日：2005-03-16

Applicant: Hiroki Katayama ,  Yoshiaki Ishigami

Inventor： Hiroki Katayama ,  Yoshiaki Ishigami

IPC: H05K7/06

CPC classification number: H05K3/3442 ,  H05K1/0239 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/09072 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10121 ,  H05K2201/10484 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10984 ,  H05K2201/2036 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic component mounted structure has: a circuit board; two semiconductor elements that are mounted on the circuit board; and an AC coupling capacitor that is operable to cut off signals with a predetermined frequency or less and is provided between the two semiconductor elements. The AC coupling capacitor is mounted on the circuit board such that a part or a whole of the AC coupling capacitor is away from the surface of the circuit board.

Abstract translation: 电子部件安装结构具有：电路板; 安装在电路板上的两个半导体元件; 以及AC耦合电容器，其可操作以以预定频率或更小的频率切断信号，并且设置在两个半导体元件之间。 AC耦合电容器安装在电路板上，使得AC耦合电容器的一部分或全部远离电路板的表面。

公开(公告)号：US20050178582A1

公开(公告)日：2005-08-18

申请号：US10964619

申请日：2004-10-15

Applicant: Sheng-Yuan Lee ,  Ya-Chi Liao

Inventor： Sheng-Yuan Lee ,  Ya-Chi Liao

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/025 ,  H05K1/0224 ,  H05K1/0231 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A circuit board with mounting pads is described for improving the frequency response of routing traces. The present invention is used to etch an etching hole on ground layer corresponding to the surface-mounted devices (SMD) on a routing layer and therefore the parasitic effect from the stray capacitor is reduced, resulting in eliminating the parasitic effect in high-frequency and raising the quality of the PCB as well.

Abstract translation: 描述了具有安装焊盘的电路板，用于改善路由迹线的频率响应。 本发明用于蚀刻对应于路由层上的表面安装器件（SMD）的接地层上的蚀刻孔，因此来自杂散电容器的寄生效应降低，从而消除了高频下的寄生效应， 提高PCB的质量。