公开(公告)号：US09666476B2

公开(公告)日：2017-05-30

申请号：US14969154

申请日：2015-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Yuping Ren ,  Duohui Bei ,  Sipeng Gu ,  Huang Liu

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/538 ,  H01L21/311 ,  H01L21/02 ,  H01L21/308 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

公开(公告)号：US09589807B1

公开(公告)日：2017-03-07

申请号：US15164146

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Jinping Liu ,  Huang Liu ,  Yuanfang Lu

IPC: H01L21/283 ,  H01L21/762 ,  H01L21/3213 ,  H01L29/66

CPC classification number: H01L21/283 ,  H01L21/32137 ,  H01L21/76224 ,  H01L21/76837 ,  H01L21/7684 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for eliminating interlayer dielectric (ILD) dishing and controlling gate height uniformity is provided. Embodiments include forming a plurality of polysilicon gates over a substrate, each gate having spacers formed on sides of the polysilicon gates and a nitride cap formed on an upper surface; forming a gapfill material between adjacent polysilicon gates; forming an oxide over the gapfill material between the adjacent polysilicon gates; removing the nitride caps; removing a portion of the oxide between the adjacent polysilicon gates, forming a recess; and forming an ILD cap layer in the recess between the adjacent polysilicon gates.

Abstract translation: 提供消除层间电介质（ILD）凹陷并控制栅极高度均匀性的方法。 实施例包括在衬底上形成多个多晶硅栅极，每个栅极具有形成在多晶硅栅极侧面上的隔离物和形成在上表面上的氮化物盖; 在相邻的多晶硅栅极之间形成间隙填充材料; 在相邻的多晶硅栅极之间的间隙填充材料上形成氧化物; 去除氮化物盖; 去除相邻多晶硅栅极之间的氧化物的一部分，形成凹陷; 以及在相邻的多晶硅栅极之间的凹槽中形成ILD覆盖层。

公开(公告)号：US20160372425A1

公开(公告)日：2016-12-22

申请号：US15247513

申请日：2016-08-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Huang Liu ,  Sarasvathi Thangaraju ,  Chun Yu Wong

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/07 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49894 ,  H01L25/072 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力的薄膜填充材料，其控制装置上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US09490129B2

公开(公告)日：2016-11-08

申请号：US14272952

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiang Hu ,  Huang Liu

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L21/28123 ,  H01L21/28035 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/32133 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/66 ,  H01L29/66553 ,  H01L29/6681

Abstract: Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures. A gate-forming material is deposited over the semiconductor substrate and fin structures. The method includes performing a first etch process to etch the gate-forming material to form a gate line having a first side and a second side. The first side and second side of the gate line are bounded with material. The method includes performing a second etch process to etch a portion of the gate line bound by the material to separate the gate line into adjacent gate structures and to define a tip-to-tip distance between the adjacent gate structures.

Abstract translation: 提供了具有改进的栅极结构的集成电路和用于制造具有改进的栅极结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有鳍结构的半导体衬底。 栅极形成材料沉积在半导体衬底和鳍结构上。 该方法包括执行第一蚀刻工艺以蚀刻栅极形成材料以形成具有第一侧和第二侧的栅极线。 栅极线的第一侧和第二侧与材料有界。 该方法包括执行第二蚀刻工艺以蚀刻由材料限定的栅极线的一部分，以将栅极线分离成相邻的栅极结构并且限定相邻栅极结构之间的尖端到尖端的距离。

公开(公告)号：US09455204B1

公开(公告)日：2016-09-27

申请号：US14727143

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy M. Cao ,  Jinping Liu ,  Guillaume Bouche ,  Huang Liu

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method of introducing N/P dopants in PMOS and NMOS fins at the SSRW layer without complicated processing and the resulting device are provided. Embodiments include forming a plurality of p-type and n-type fins on a substrate, the plurality of p-type and n-type fins formed with an ISSG or pad oxide layer; performing an n-well implant into the substrate through the ISSG or pad oxide layer; performing a first SRPD on the ISSG or pad oxide layer of the plurality of p-type fins; performing a p-well implant into the substrate through the ISSG or pad oxide layer; performing a second SRPD on the ISSG or pad oxide layer of the plurality of n-type fins; and driving the n-well and p-well implants and the SRPD dopants into a portion of the plurality of p-type and n-type fins.

Abstract translation: 在SSRW层的PMOS和NMOS鳍片中引入N / P掺杂剂而不需要复杂的处理并提供所得到的器件的方法。 实施例包括在基板上形成多个p型和n型翅片，多个p型和n型翅片形成有ISSG或衬垫氧化物层; 通过ISSG或衬垫氧化物层将n阱注入到衬底中; 在多个p型翅片的ISSG或衬垫氧化物层上执行第一SRPD; 通过ISSG或垫氧化物层进行p阱注入到衬底中; 在所述多个n型鳍片的ISSG或衬垫氧化物层上执行第二SRPD; 并且将n阱和p阱注入和SRPD掺杂剂驱动到多个p型和n型鳍中的一部分中。

公开(公告)号：US09431528B2

公开(公告)日：2016-08-30

申请号：US14281359

申请日：2014-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Xiang Hu ,  Zhao Lun ,  Huang Liu

IPC: H01L21/311 ,  H01L29/06 ,  H01L29/12 ,  H01L29/78 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/0684 ,  H01L29/12 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A lithographic stack over a raised structure (e.g., fin) of a non-planar semiconductor structure, such as a FinFET, includes a bottom layer of spin-on amorphous carbon or spin-on organic planarizing material, a hard mask layer of a nitride and/or an oxide on the spin-on layer, a layer of a developable bottom anti-reflective coating (dBARC) on the hard mask layer, and a top layer of photoresist. The stack is etched to expose and recess the raised structure, and epitaxial structure(s) are grown on the recess.

Abstract translation: 诸如FinFET的非平面半导体结构的凸起结构（例如，翅片）上的光刻叠层包括旋涂非晶碳或旋涂有机平面化材料的底层，氮化物的硬掩模层 和/或旋涂层上的氧化物，硬掩模层上的可显影底部抗反射涂层（dBARC）的层和光致抗蚀剂的顶层。 蚀刻该叠层以露出和凹进凸起的结构，并且外延结构在凹槽上生长。

公开(公告)号：US20160211373A1

公开(公告)日：2016-07-21

申请号：US15080369

申请日：2016-03-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： HONG YU ,  Hyucksoo Yang ,  Huang Liu ,  Richard J. Carter

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/24 ,  H01L29/267 ,  H01L21/8238 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/8238 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.

公开(公告)号：US20150333121A1

公开(公告)日：2015-11-19

申请号：US14810167

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US20150325482A1

公开(公告)日：2015-11-12

申请号：US14272952

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiang Hu ,  Huang Liu

IPC: H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/088 ,  H01L21/308

CPC classification number: H01L21/28123 ,  H01L21/28035 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/32133 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/66 ,  H01L29/66553 ,  H01L29/6681

Abstract: Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures. A gate-forming material is deposited over the semiconductor substrate and fin structures. The method includes performing a first etch process to etch the gate-forming material to form a gate line having a first side and a second side. The first side and second side of the gate line are bounded with material. The method includes performing a second etch process to etch a portion of the gate line bound by the material to separate the gate line into adjacent gate structures and to define a tip-to-tip distance between the adjacent gate structures.

Abstract translation: 提供了具有改进的栅极结构的集成电路和用于制造具有改进的栅极结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有鳍结构的半导体衬底。 栅极形成材料沉积在半导体衬底和鳍结构上。 该方法包括执行第一蚀刻工艺以蚀刻栅极形成材料以形成具有第一侧和第二侧的栅极线。 栅极线的第一侧和第二侧与材料有界。 该方法包括执行第二蚀刻工艺以蚀刻由材料限定的栅极线的一部分，以将栅极线分离成相邻的栅极结构并且限定相邻栅极结构之间的尖端到尖端的距离。

公开(公告)号：US20140315385A1

公开(公告)日：2014-10-23

申请号：US13868412

申请日：2013-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hung-Wei Liu ,  Tsung-Liang Chen ,  Huang Liu ,  Zhiguo Sun

IPC: H01L21/02

CPC classification number: H01L21/02112 ,  H01L21/02129 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/76837

Abstract: A method for flowable oxide deposition is provided. An oxygen source gas is increased as a function of time or film depth to change the flowable oxide properties such that the deposited film is optimized for gap fill near a substrate surface where high aspect ratio shapes are present. The oxygen gas flow rate increases as the film depth increases, such that the deposited film is optimized for planarization quality at the upper regions of the deposited film.

Abstract translation: 提供了一种可流动氧化物沉积的方法。 作为时间或膜深度的函数，氧源气体增加以改变可流动的氧化物性质，使得沉积膜针对存在高纵横比形状的衬底表面附近的间隙填充进行了优化。 氧气流速随着膜深度的增加而增加，使得沉积膜对沉积膜的上部区域的平坦化质量进行了优化。