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    Look-ahead hash chain matching for data compression
    23.
    发明授权
    Look-ahead hash chain matching for data compression 有权

    公开(公告)号：US09768802B2

    公开(公告)日：2017-09-19

    申请号：US15406133

    申请日：2017-01-13

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/00 ,  H03M7/30 ,  H03M7/42

    CPC classification number: H03M7/3086 ,  H03M7/42

    Abstract: Example data compression methods disclosed herein include determining a first hash chain index corresponding to a first position in an input data buffer based on a first group of bytes accessed from the input data buffer beginning at a first look-ahead offset from the first position. If a first hash chain (indexed by the first hash chain index), does not satisfy a quality condition, a second hash chain index corresponding to the first position in the input data buffer based on a second group of bytes accessed from the input data buffer beginning at a second look-ahead offset from the first position is determined. The input data buffer is searched at respective adjusted buffer positions to find a second string of data bytes matching a first string of data bytes and information related to the second string of data bytes is provided to an encoder to output compressed data.

    COHERENT FABRIC INTERCONNECT FOR USE IN MULTIPLE TOPOLOGIES
    27.
    发明申请
    COHERENT FABRIC INTERCONNECT FOR USE IN MULTIPLE TOPOLOGIES 有权
    用于多种拓扑学的相容织物互连

    公开(公告)号：US20160378701A1

    公开(公告)日：2016-12-29

    申请号：US14751899

    申请日：2015-06-26

    Applicant: Intel Corporation

    Inventor： Jose S. Niell ,  Daniel F. Cutter ,  Stephen J. Robinson ,  Mukesh K. Patel

    IPC: G06F13/28 ,  G06F12/08 ,  G06F13/40

    CPC classification number: G06F13/28 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0868 ,  G06F13/4068 ,  G06F2212/1032 ,  G06F2212/608

    Abstract: An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus comprises mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, where the fabric comprises logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative.

    Abstract translation: 公开了一种具有支撑多种拓扑结构的结构互连的装置及其使用方法。 在一个实施例中，该装置包括用于存储指示多个模式之一的信息的模式存储器; 以及可以多种模式操作的第一结构，其中所述结构包括耦合到所述模式存储器的逻辑，以根据由所述信息指示识别的模式来控制对由所述第一结构接收的存储器的读取和写入请求的处理。

    Managing state data in a compression accelerator
    28.
    发明授权
    Managing state data in a compression accelerator 有权

    公开(公告)号：US10404836B2

    公开(公告)日：2019-09-03

    申请号：US15390579

    申请日：2016-12-26

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Daniel F. Cutter

    IPC: H04L29/06

    Abstract: In an embodiment, a processor comprises a plurality of processing cores and a compression accelerator to compress an input stream comprising a first data block and a second data block. The compression accelerator comprises a first compression engine to compress the first data block; and a second compression engine to update state data for the second compression engine using a sub-portion of the first data block; and after an update of the state data for the second compression engine using the sub-portion of the first data block, compress a second data block using the updated state data for the second compression engine. Other embodiments are described and claimed.

    Techniques for data compression verification
    29.
    发明授权
    Techniques for data compression verification 有权

    公开(公告)号：US10224959B2

    公开(公告)日：2019-03-05

    申请号：US15935117

    申请日：2018-03-26

    Applicant: INTEL CORPORATION

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Kirk S. Yap ,  Daniel F. Cutter ,  Wajdi K. Feghali

    IPC: H03M7/40 ,  H03M7/30 ,  H04L1/24

    Abstract: Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.

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