公开(公告)号：US20210143265A1

公开(公告)日：2021-05-13

申请号：US17154755

申请日：2021-01-21

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US10998423B2

公开(公告)日：2021-05-04

申请号：US16881549

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Van H. Le ,  Scott B. Clendenning ,  Martin M. Mitan ,  Szuya S. Liao

IPC: H01L29/66 ,  B82Y10/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/762

Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.

公开(公告)号：US10243080B2

公开(公告)日：2019-03-26

申请号：US15527288

申请日：2014-12-19

Applicant: INTEL CORPORATION

Inventor： Grant Kloster ,  Scott B. Clendenning ,  Rami Hourani ,  Szuya S. Liao ,  Patricio E. Romero ,  Florian Gstrein

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L29/786 ,  H01L21/32 ,  H01L23/498

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

公开(公告)号：US09932671B2

公开(公告)日：2018-04-03

申请号：US15119699

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Patricio E. Romero ,  Scott B. Clendenning ,  Grant M. Kloster ,  Florian Gstrein ,  Harsono S. Simka ,  Paul A. Zimmerman ,  Robert L. Bristol

IPC: H01L21/336 ,  C23C16/455 ,  C23C16/18 ,  C23C16/48 ,  H01L21/768 ,  H01L21/285 ,  H01L29/66 ,  H01L21/033

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/482 ,  H01L21/0337 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/66795

Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.

公开(公告)号：US09928966B2

公开(公告)日：2018-03-27

申请号：US13730324

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Zhaohui Chen ,  Donald S. Gardner ,  Bum Ki Moon ,  Charles W. Holzwarth ,  Cary L. Pint ,  Scott B. Clendenning

IPC: H05K1/18 ,  H01G11/24 ,  G11C13/00 ,  H01L49/02

CPC classification number: H01G11/24 ,  G11C13/0002 ,  G11C13/0016 ,  H01L28/82 ,  Y02E60/13 ,  Y10T29/435

Abstract: In one embodiment, a structure for an energy storage device may include a first nanostructured substrate having a conductive layer and a dielectric layer formed on the conductive layer. A second nanostructured substrate includes another conductive layer. A separator separates the first and second nanostructured substrates and allows ions of an electrolyte to pass through the separator. The structure may be a nanostructured electrolytic capacitor with the first nanostructured substrate forming a positive electrode and the second nanostructured substrate forming a negative electrode of the capacitor.

公开(公告)号：US20180082942A1

公开(公告)日：2018-03-22

申请号：US15560245

申请日：2015-04-29

Applicant: INTEL CORPORATION

Inventor： Jasmeet S. Chawla ,  Rami Hourani ,  Mauro J. Kobrinsky ,  Florian Gstrein ,  Scott B. Clendenning ,  Jeanette M. Roberts

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2221/101 ,  H01L2221/1063

Abstract: A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.

公开(公告)号：US09455150B2

公开(公告)日：2016-09-27

申请号：US14140042

申请日：2013-12-24

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Patricio E. Romero ,  Gilbert Dewey

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/45 ,  H01L29/49 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L21/28088 ,  H01L21/28176 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: The present disclosure relates to a method of forming a semiconductor. The method includes heating a substrate in a reaction chamber, supplying to the reaction chamber a first constituent including a metal borohydride wherein the metal borohydride includes at least one of: an alkaline earth metal, a transition metal, or a combination thereof; supplying to the reaction chamber a main-group hydride constituent; and depositing a metal compound on the substrate, wherein the metal compound comprises a) at least one of an alkaline earth metal a transition metal or a combination thereof, b) boron and c) optionally the main group alloying element.

Abstract translation: 本公开涉及形成半导体的方法。 该方法包括加热反应室中的基材，向反应室供应包括金属硼氢化物的第一组分，其中金属硼氢化物包括以下中的至少一种：碱土金属，过渡金属或其组合; 向反应室供应主要的氢化物组分; 以及在基底上沉积金属化合物，其中金属化合物包括a）碱土金属过渡金属或其组合中的至少一种，b）硼和c）任选的主族合金元素。

公开(公告)号：US20250113572A1

公开(公告)日：2025-04-03

申请号：US18375060

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Uygar E. Avci ,  Kevi P. Obrien ,  Chia-Ching Lin ,  Carl H. Naylor ,  Kirby Maxey ,  Andrey Vyatskikh ,  Scott B. Clendenning ,  Matthew Metz ,  Marko Radosavljevic

IPC: H01L29/18 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Techniques and mechanisms for forming a gate dielectric structure and source or drain (S/D) structures on a monolayer channel structure of a transistor. In an embodiment, the channel structure comprises a two-dimensional (2D) layer of a transition metal dichalcogenide (TMD) material. During fabrication of the transistor structure, a layer of a dielectric material is deposited on the channel structure, wherein the dielectric material is suitable to provide a reaction, with a plasma, to produce a conductive material. While a first portion of the dielectric material is covered by a patterned structure, a second portion of the dielectric material is exposed to a plasma treatment to form a source or dielectric (S/D) electrode structure that adjoins the first portion. In another embodiment, the dielectric material is an oxide of a Group V-VI transition metal.

公开(公告)号：US20250006841A1

公开(公告)日：2025-01-02

申请号：US18345127

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Rachel A. Steinhardt ,  Punyashloka Debashis ,  Kevin P. O'Brien ,  Matthew V. Metz ,  Scott B. Clendenning ,  Brandon Holybee ,  Marko Radosavljevic ,  Ian Alexander Young ,  I-Cheng Tung ,  Sudarat Lee ,  Raseong Kim ,  Pratyush P. Buragohain

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/221 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.

公开(公告)号：US12183739B2

公开(公告)日：2024-12-31

申请号：US17127280

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Nicole Thomas ,  Eric Mattson ,  Sudarat Lee ,  Scott B. Clendenning ,  Tobias Brown-Heft ,  I-Cheng Tung ,  Thoe Michaelos ,  Gilbert Dewey ,  Charles Kuo ,  Matthew Metz ,  Marko Radosavljevic ,  Charles Mokhtarzadeh

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.