公开(公告)号：US20240071860A1

公开(公告)日：2024-02-29

申请号：US18502162

申请日：2023-11-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Jerome TEYSSEYRE

IPC: H01L23/373 ,  H01L21/52 ,  H01L23/00 ,  H01L23/31 ,  H01L23/433 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L23/3735 ,  H01L21/52 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4334 ,  H01L23/49822 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/50 ,  H01L29/861

Abstract: In a general aspect, a package includes a semiconductor die disposed between a first high voltage isolation carrier and a second high voltage isolation carrier. The semiconductor die is thermally coupled to the first high voltage isolation carrier. The package also includes a molding material disposed in a space between the semiconductor die and the first high voltage isolation carrier, and a conductive spacer disposed between the semiconductor die and the second high voltage isolation carrier. The conductive spacer is thermally coupled to semiconductor die and to the second high voltage isolation carrier. A longitudinal dimension of the conductive spacer is greater than a longitudinal dimension of the semiconductor die. The molding material encapsulates the semiconductor die and the conductive spacer.

公开(公告)号：US20230064356A1

公开(公告)日：2023-03-02

申请号：US17822403

申请日：2022-08-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Swarnal BORTHAKUR ,  Larry Duane KINSMAN

IPC: H01L27/146

Abstract: A package includes an interposer substrate having at least one through-substrate via (TSV) electrically connecting a top surface of the interposer substrate to a bottom surface of the interposer substrate. The package further includes at least one semiconductor die having a top side, a bottom side, and a sidewall. The at least one semiconductor die is disposed on the interposer substrate with the bottom side electrically coupled to the top surface of the interposer substrate. A molding material is disposed on at least on a portion of the at least one semiconductor die, and an array of conductive material is disposed on the bottom surface of the interposer substrate. The array of conductive material forms the external contacts of the package.

公开(公告)号：US20220415766A1

公开(公告)日：2022-12-29

申请号：US17929884

申请日：2022-09-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L23/40 ,  H01L23/367

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

公开(公告)号：US20210035807A1

公开(公告)日：2021-02-04

申请号：US17072521

申请日：2020-10-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Michael J. SEDDON ,  Francis J. CARNEY ,  Takashi NOMA ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/12 ,  H01L23/00 ,  H01L21/78

Abstract: Implementations of a semiconductor package may include a semiconductor die including a first side and a second side where the first side of the semiconductor die includes one or more electrical contacts; a layer of metal coupled to the second side of the semiconductor; and a stress balance structure coupled to one of the layer of metal or around the one or more electrical contacts.

公开(公告)号：US20200279747A1

公开(公告)日：2020-09-03

申请号：US16879378

申请日：2020-05-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Yusheng LIN ,  Michael J. SEDDON ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/12 ,  H01L23/00 ,  H01L21/78

Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

公开(公告)号：US20200144200A1

公开(公告)日：2020-05-07

申请号：US16181876

申请日：2018-11-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erik Nino TOLENTINO ,  Chee Hiong CHEW ,  Yusheng LIN ,  Swee Har KHOR

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/78

Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.

公开(公告)号：US20190252275A1

公开(公告)日：2019-08-15

申请号：US16396904

申请日：2019-04-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Chee Hiong CHEW ,  Francis J. CARNEY

IPC: H01L23/055 ,  H01L23/498 ,  H01L23/053 ,  H01L25/07 ,  H01L23/04 ,  H01L23/492 ,  H01L21/50 ,  H01L23/00 ,  H01R4/48 ,  H01L23/50 ,  H01L23/10 ,  H01L23/057

CPC classification number: H01L23/055 ,  H01L21/50 ,  H01L23/041 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/4006 ,  H01L23/492 ,  H01L23/49811 ,  H01L23/49844 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/72 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/72 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01R4/4863 ,  H01R4/489 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

公开(公告)号：US20180254243A1

公开(公告)日：2018-09-06

申请号：US15973904

申请日：2018-05-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Yenting WEN ,  George CHANG

IPC: H01L23/528 ,  H01L21/78 ,  H01L23/522 ,  H01L23/36 ,  H01L23/532 ,  H01L21/50 ,  H01L21/304

CPC classification number: H01L23/528 ,  H01L21/304 ,  H01L21/50 ,  H01L21/78 ,  H01L23/36 ,  H01L23/492 ,  H01L23/5228 ,  H01L23/53228

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

公开(公告)号：US20180240786A1

公开(公告)日：2018-08-23

申请号：US15954353

申请日：2018-04-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jinchang ZHOU ,  Yusheng LIN ,  Mingjiao LIU

IPC: H01L25/07 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/11 ,  H01L25/00 ,  H01L29/739 ,  H01L41/083

CPC classification number: H01L25/071 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/074 ,  H01L25/117 ,  H01L25/50 ,  H01L29/7395 ,  H01L41/083 ,  H01L2224/0401 ,  H01L2224/05085 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/1403 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/92242 ,  H01L2225/06503 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19105

Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.

公开(公告)号：US20180005936A1

公开(公告)日：2018-01-04

申请号：US15198799

申请日：2016-06-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Yenting WEN ,  George CHANG

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/36 ,  H01L21/78 ,  H01L21/50 ,  H01L23/532 ,  H01L21/304

CPC classification number: H01L23/528 ,  H01L21/304 ,  H01L21/50 ,  H01L21/78 ,  H01L23/36 ,  H01L23/492 ,  H01L23/5228 ,  H01L23/53228

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.