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    High wireability microvia substrate
    21.
    发明申请
    High wireability microvia substrate 有权
    高线性微孔板

    公开(公告)号：US20060012054A1

    公开(公告)日：2006-01-19

    申请号：US11233572

    申请日：2005-09-23

    申请人： Irving Memis

    发明人： Irving Memis

    IPC分类号： H01L23/48

    CPC分类号： H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10674 ,  H01L2924/00

    摘要： The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip through the core to the bottom surface where signals exit the carrier to the printed wiring board, which is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip, thereby increasing the density of circuits escaping the footprint area.

    摘要翻译： 通过将来自芯片的信号重新定位到载体的上部信号层，可以改善信号从倒装芯片/球栅阵列组件中的半导体芯片到印刷线路板的逸出。 这涉及通过芯片载体将电路线从通过芯到芯片的芯片通过芯片的顶表面扇出，信号从载体离开印刷电路板，这是通过更好地利用表面积来实现的 核心和芯片之间的信号平面。 信号在每个顶部信号平面上被扇出，使得更多的信号通过芯中的通孔传输到底部信号平面，在那里它们可以逃逸到芯片的覆盖区域之外，从而增加了 电路逃离占地面积。

    HIGH DENSITY MICROVIA SUBSTRATE WITH HIGH WIREABILITY
    24.
    发明申请
    HIGH DENSITY MICROVIA SUBSTRATE WITH HIGH WIREABILITY 失效
    高密度高密度微晶基材

    公开(公告)号：US20050093133A1

    公开(公告)日：2005-05-05

    申请号：US10701311

    申请日：2003-11-04

    申请人： Kazushige Kawasaki ,  Irving Memis

    发明人： Kazushige Kawasaki ,  Irving Memis

    IPC分类号： H05K1/18 ,  H01L23/12 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H01L29/40

    CPC分类号： H01L23/49838 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/029 ,  H05K2201/09609 ,  H05K2201/09627

    摘要： The density of plated thru holes in a glass fiber based chip carrier is increased by off-setting holes to positions in which fibers from adjacent holes will not connect. Elongated strip zones or regions having a width approximately the diameter of the holes and running along orthogonal columns and rows of holes, parallel to the direction of fibers, define regions of fibers that can possibly cause shorting between holes. Rotating a conventional X-Y grid pattern of equidistant holes so as to position, for example, alternate holes in one direction between the elongated strip zones running in the opposite direction significantly increases the distance between holes along the elongated strip zones running in each direction. The holes are positioned between elongated strip zones with sufficient clearance to compensate for variations in the linear path of fibers.

    摘要翻译： 基于玻璃纤维的芯片载体中的电镀通孔的密度通过偏移孔增加到相邻孔的纤维将不连接的位置。 宽度大约为孔的宽度的区域或区域平行于纤维方向的正交列和孔排沿着孔的直径延伸，限定了可能导致孔之间短路的纤维区域。 旋转等距孔的常规X-Y网格图案，以便例如在沿相反方向运行的细长条带之间的一个方向上的交替孔定位显着地增加沿着沿每个方向运行的细长条带的孔之间的距离。 孔位于具有足够间隙的细长带区之间以补偿纤维线性路径的变化。

    Method of making circuitized substrate with improved impedance control circuitry, electrical assembly and information handling system
    26.
    发明授权
    Method of making circuitized substrate with improved impedance control circuitry, electrical assembly and information handling system 失效
    具有改进的阻抗控制电路，电气组装和信息处理系统的电路化衬底的方法

    公开(公告)号：US07589283B2

    公开(公告)日：2009-09-15

    申请号：US11889668

    申请日：2007-08-15

    申请人： Charles E. Danoski ,  Irving Memis ,  Steven G. Rosser

    发明人： Charles E. Danoski ,  Irving Memis ,  Steven G. Rosser

    IPC分类号： H05K1/16

    CPC分类号： H01L23/66 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/093 ,  H05K2201/09627 ,  H05K2201/09663 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

    摘要： A method of making a circuitized substrate designed to substantially eliminate impedance disruptions during passage of signals through signal lines of the substrate's circuitry. The produced substrate includes a first conductive layer with a plurality of conductors on which an electrical component may be positioned and electrically coupled. The pads are coupled to signal lines (e.g., using thru-holes) further within the substrate and these signal lines are further coupled to a second plurality of conductive pads located even further within the substrate. The signal lines are positioned so as to lie between the substrate's first conductive layer and a voltage plane within a third conductive layer below the second conductive layer including the signal lines. A second voltage plane may be used adjacent the first voltage plane of the third conductive layer. Thru-holes may also be used to couple the signal lines coupled to the first conductors to a second plurality of conductors which form part of the third conductive layer. An electrical assembly and information handling system (e.g., computer) utilizing the substrate are also disclosed.

    摘要翻译： 制造电路化衬底的方法被设计为基本上消除信号通过衬底电路的信号线时的阻抗中断。 所生产的衬底包括具有多个导体的第一导电层，电组件可在其上定位并电耦合。 这些焊盘在衬底内进一步耦合到信号线（例如，使用通孔），并且这些信号线还被进一步耦合到位于衬底内的另外多个导电衬垫。 信号线被定位成位于衬底的第一导电层和位于包括信号线的第二导电层下面的第三导电层内的电压平面之间。 可以在第三导电层的第一电压平面附近使用第二电压平面。 通孔也可用于将耦合到第一导体的信号线耦合到形成第三导电层的一部分的第二多个导体。 还公开了利用该基板的电组件和信息处理系统（例如，计算机）。

    High performance chip carrier substrate
    27.
    发明授权
    High performance chip carrier substrate 失效
    高性能芯片载体基板

    公开(公告)号：US07454833B2

    公开(公告)日：2008-11-25

    申请号：US11651631

    申请日：2007-01-09

    申请人： Jean Audet ,  Irving Memis

    发明人： Jean Audet ,  Irving Memis

    IPC分类号： H05K3/00 ,  H05K3/10

    CPC分类号： H05K1/112 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y10T29/49155 ,  Y10T29/4916

    摘要： A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.

    摘要翻译： 一种多层芯片载体，增加了配电PTH的空间，降低了功率相关噪声。 在具有两个信号再分配扇出层的多层芯片载体中，除了信号从第一扇出层附近的边缘信号焊盘逸出，剩余的信号焊盘移动到更靠近芯片覆盖区的边缘。 在第一扇出层下方的电压层，剩余的信号垫再次移动，更靠近芯片占位面的边缘。 在第二扇出层中，电压层以下，剩余的信号垫排出。 信号垫移动的区域为功率PTH提供了增加的空间。

    High wireability microvia substrate
    29.
    发明授权
    High wireability microvia substrate 有权
    高线性微孔板

    公开(公告)号：US07279798B2

    公开(公告)日：2007-10-09

    申请号：US11233572

    申请日：2005-09-23

    申请人： Irving Memis

    发明人： Irving Memis

    IPC分类号： H01L23/52

    CPC分类号： H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10674 ,  H01L2924/00

    摘要： The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip through the core to the bottom surface where signals exit the carrier to the printed wiring board, which is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip, thereby increasing the density of circuits escaping the footprint area.

    摘要翻译： 通过将来自芯片的信号重新定位到载体的上部信号层，可以改善信号从倒装芯片/球栅阵列组件中的半导体芯片到印刷线路板的逸出。 这涉及通过芯片载体将电路线从通过芯到芯片的芯片通过芯片的顶表面扇出，信号从载体离开印刷电路板，这是通过更好地利用表面积来实现的 核心和芯片之间的信号平面。 信号在每个顶部信号平面上扇出，使得更多的信号通过芯中的通孔传输到底部信号平面，在那里它们可以逃逸到芯片的覆盖区域之外，从而增加了 电路逃离占地面积。