公开(公告)号：US20180158762A1

公开(公告)日：2018-06-07

申请号：US15688572

申请日：2017-08-28

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tatsuo TONEDACHI

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49555 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L2224/29147 ,  H01L2224/32245 ,  H01L2224/33 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device includes a semiconductor chip having a first surface, a first electrode and a second electrode provided on the first surface, a wiring electrically connected to the first electrode at the first surface, a first metal layer on the first surface and directly contacting the second electrode, a thickness of the first metal layer in a direction orthogonal to the first surface being greater than a height of a topmost portion of the wiring in the first direction from the first surface, and a resin package contacting the semiconductor chip, the first metal layer, at least a portion of the wiring, and a first portion of the first surface and leaving a second portion of the first surface exposed.

公开(公告)号：US09978670B2

公开(公告)日：2018-05-22

申请号：US15503438

申请日：2014-11-27

Applicant: Mitsubishi Electric Corporation

Inventor： Shunsuke Fushie ,  Yoshihito Asao ,  Yu Kawano ,  Akihiko Mori

IPC: H01L23/495 ,  H01L23/28 ,  H01L23/50 ,  H01L23/367 ,  H01L23/498 ,  H01L23/528

CPC classification number: H01L23/49568 ,  H01L23/28 ,  H01L23/3672 ,  H01L23/4334 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/49861 ,  H01L23/50 ,  H01L23/5283 ,  H01L23/5286 ,  H01L25/072 ,  H01L2224/0603 ,  H01L2224/37147 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor module forming a semiconductor device includes lead frames in which switching elements are mounted on the side of upper surfaces and heat radiation surfaces are formed on the side of lower surfaces, and bus bars disposed on the lead frames and connecting between plural switching elements. The heat radiation surfaces of the lead frames are arranged on one plane and upper surfaces of flat surface portions of the bus bars are arranged on one plane, therefore, a layout property on the heat radiation surfaces or the upper surfaces the flat surface portions is good, which facilitates creation of a heat radiation structure and so on.

公开(公告)号：US09972562B2

公开(公告)日：2018-05-15

申请号：US15471472

申请日：2017-03-28

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/4832 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device includes: a semiconductor die having first and second opposite surfaces, a die pad having the first surface of the semiconductor die attached thereon, an electrically conductive ground pad at the second surface of the semiconductor die, a device package coupled with the semiconductor die with the ground pad lying between the semiconductor die and the package, and ground wiring or tracks for the semiconductor die between the second surface of the semiconductor die and the ground pad. A further ground connection may be provided between the ground pad at the second surface of the semiconductor die and the die pad having the semiconductor die attached thereon.

公开(公告)号：US20180130725A1

公开(公告)日：2018-05-10

申请号：US15868798

申请日：2018-01-11

Applicant: ROHM CO., LTD.

Inventor： Shoji YASUNAGA ,  Mamoru YAMAGAMI

IPC: H01L23/495 ,  H01L23/373 ,  H01L23/31

CPC classification number: H01L23/49568 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0612 ,  H01L2224/06505 ,  H01L2224/14104 ,  H01L2224/145 ,  H01L2224/1451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4912 ,  H01L2224/495 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2924/01013 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/12042 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: [Object] A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution] A semiconductor device includes: a die pad 11 which has a die pad main surface 111 and a die pad rear surface 112; a semiconductor chip 41 mounted on the die pad main surface 111; a sealing resin portion 7 formed with a recess 75 for exposure of the die pad rear surface 11 and covering the die pad 11 and the semiconductor chip 41; and a heat releasing layer 6 disposed in the recess 75. The recess 75 has a recess groove 753 outside the die pad 11 in a direction in which the die pad rear surface 112 extends, and the recess groove 753 is closer to the die pad main surface 111 than to the die pad rear surface 112. The heat releasing layer 6 has a junction layer which is in contact with the die pad rear surface 112 and having part thereof filling the recess groove 753.

公开(公告)号：US09960096B2

公开(公告)日：2018-05-01

申请号：US14917618

申请日：2014-09-09

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Tomomi Okumura ,  Takuya Kadoguchi

IPC: H01L23/051 ,  H01L23/367 ,  H01L25/07 ,  H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/433 ,  H01L23/495

CPC classification number: H01L23/3672 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4334 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/33 ,  H01L25/07 ,  H01L25/18 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In a semiconductor device, a second heat sink and a third heat sink are electrically connected by a joint portion in an alignment direction in which a first switching element and a second switching element are aligned. A second power-supply terminal is disposed in the alignment direction in a region between a first power-supply terminal and an output terminal and between the second heat sink and the third heat sink. In an encapsulation resin body, at least one of a shortest distance between a first potential portion at same potential as the first power-supply terminal and a third potential portion at same potential as the output terminal and a shortest distance between a second potential portion at same potential as the second power-supply terminal and the third potential portion is shorter than a shortest distance between the first potential portion and the second potential portion.

公开(公告)号：US20180114783A1

公开(公告)日：2018-04-26

申请号：US15787712

申请日：2017-10-19

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L25/10 ,  H01L23/04 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors.

公开(公告)号：US20180114704A1

公开(公告)日：2018-04-26

申请号：US15782862

申请日：2017-10-13

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

公开(公告)号：US09953910B2

公开(公告)日：2018-04-24

申请号：US12061141

申请日：2008-04-02

Applicant: Charles Gerard Woychik ,  Raymond Albert Fillion

Inventor： Charles Gerard Woychik ,  Raymond Albert Fillion

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49822 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/31 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81801 ,  H01L2224/83132 ,  H01L2224/92144 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16195 ,  Y10T428/26 ,  Y10T428/31515 ,  Y10T428/31663 ,  Y10T428/31678 ,  H01L2924/00 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014

Abstract: An electronic component includes a base insulative layer having first and second surfaces; an electronic device having first and second surfaces; at least one I/O contact located on the first surface of the electronic device; an adhesive layer disposed between the first surface of the electronic device and the second surface of the base insulative layer; a first metal layer disposed on the I/O contact; and a removable layer disposed between the first surface of the electronic device and the second surface of the base insulative layer, and located adjacent to the first metal layer. The base insulative layer secures to the electronic device through the first metal layer and removable layer. The first metal layer and removable layer can release the base insulative layer from the electronic device when the first metal layer and removable layer are exposed to a temperature higher than their softening points or melting points.

公开(公告)号：US09953903B2

公开(公告)日：2018-04-24

申请号：US14806526

申请日：2015-07-22

Applicant: NXP B.V.

Inventor： Leonardus Antonius Elisabeth van Gemert ,  Tonny Kamphuis ,  Rintje van der Meulen ,  Emil Casey Israel

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/433 ,  H01L21/78 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49568 ,  H01L21/4821 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/20752

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.

公开(公告)号：US09947752B2

公开(公告)日：2018-04-17

申请号：US15601180

申请日：2017-05-22

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Akitaka Soeno

IPC: H01L29/41

CPC classification number: H01L29/41 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/4334 ,  H01L2224/33

Abstract: A semiconductor device may include a semiconductor substrate, a first metal film covering a surface of the semiconductor substrate; a protection film covering a peripheral portion of a surface of the first metal film; and a second metal film covering a range extending across a center portion of the surface of the first metal film and a surface of the protection film, wherein a recess may be provided in the surface of the protection film, and a part of the second metal film may be in contact with an inner surface of the recess.