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    Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof
    32.
    发明授权
    Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof 有权
    引线框半导体封装结构的倒装芯片及其制造方法

    公开(公告)号：US09502337B2

    公开(公告)日：2016-11-22

    申请号：US14926649

    申请日：2015-10-29

    申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD.

    发明人： Lei Shi

    IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00 ,  H01L21/60

    CPC分类号： H01L23/49558 ,  H01L21/4825 ,  H01L21/4835 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2021/60022 ,  H01L2924/18161

    摘要： Flip-chip on leadframe (FCOL) semiconductor packaging structure and fabrication method thereof are provided. A semiconductor chip with copper pillars formed there-over is provided. A barrier layer is formed on the copper pillars. A solder material is coated on the barrier layer. A layer of soldering flux is coated on the solder material. A leadframe with electric leads formed thereon is provided. An insulating layer is formed an the leadframe and having a plurality of openings to expose portion of the electric leads. The semiconductor chip is placed upside down onto the leadframe to have the soldering flux in contact with the portion of the electric leads exposed in the openings. The solder material flows back to form conductive interconnections between the copper pillars and the portion of the electric leads exposed in the openings. The semiconductor chip is packaged with the leadframe using a mold compound.

    摘要翻译： 提供了引线框倒装芯片（FCOL）半导体封装结构及其制造方法。 提供了一种在其上形成铜柱的半导体芯片。 在铜柱上形成阻挡层。 焊料材料涂覆在阻挡层上。 一层焊剂焊接在焊料上。 提供了形成有电引线的引线框架。 绝缘层形成为引线框架并且具有多个开口以暴露电引线的部分。 半导体芯片被倒置放置在引线框架上，以使焊剂与暴露在开口中的电引线的部分接触。 焊料材料流回到铜柱和暴露在开口中的电引线部分之间的导电互连。 使用模具化合物将半导体芯片与引线框架封装。

    Method and structure for wafer-level packaging
    34.
    发明授权
    Method and structure for wafer-level packaging 有权
    晶圆级封装的方法和结构

    公开(公告)号：US09437511B2

    公开(公告)日：2016-09-06

    申请号：US14964869

    申请日：2015-12-10

    申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD.

    发明人： Jiangen Shi

    IPC分类号： H01L23/544 ,  H01L23/31 ,  H01L21/82 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

    CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/53228 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/94 ,  H01L2224/03

    摘要： A method for wafer-level packaging includes providing a semiconductor wafer having a plurality of semiconductor chips connected by connection stems in the wafer. The method further includes forming a plurality of through holes in the connections stems; forming a protective layer covering the wafer with a plurality of positions for planting soldering balls exposed. The protective layer includes an upper protective layer formed on a top side of the wafer, a lower protective layer formed on a back side of the wafer, and a plurality of middle protective layers formed in the through holes. The upper protective layer is connected to the lower protective layer through the plurality of the middle protective layers. The method also includes forming soldering balls on the positions for planting soldering balls and finally, forming a plurality of packaged individual semiconductor chip structures by cutting the wafer along the connection stems with the through holes.

    摘要翻译： 一种用于晶片级封装的方法包括提供具有通过晶片中的连接杆连接的多个半导体芯片的半导体晶片。 该方法还包括在连接杆中形成多个通孔; 形成覆盖晶片的保护层，其具有用于种植暴露的焊球的多个位置。 保护层包括形成在晶片的上侧的上保护层，形成在晶片背面的下保护层和形成在通孔中的多个中间保护层。 上保护层通过多个中间保护层连接到下保护层。 该方法还包括在用于种植焊球的位置上形成焊球，最后通过沿着连接杆与通孔切割晶片来形成多个封装的单个半导体芯片结构。

    FLIP-CHIP ON LEADFRAME SEMICONDUCTOR PACKAGING STRUCTURE AND FABRICATION METHOD THEREOF
    36.
    发明申请
    FLIP-CHIP ON LEADFRAME SEMICONDUCTOR PACKAGING STRUCTURE AND FABRICATION METHOD THEREOF 有权
    铅笔半导体封装结构及其制造方法

    公开(公告)号：US20160126166A1

    公开(公告)日：2016-05-05

    申请号：US14926649

    申请日：2015-10-29

    申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD.

    发明人： LEI SHI

    IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56

    CPC分类号： H01L23/49558 ,  H01L21/4825 ,  H01L21/4835 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2021/60022 ,  H01L2924/18161

    摘要： Flip-chip on leadframe (FCOL) semiconductor packaging structure and fabrication method thereof are provided. A semiconductor chip with copper pillars formed there-over is provided. A barrier layer is formed on the copper pillars. A solder material is coated on the barrier layer. A layer of soldering flux is coated on the solder material. A leadframe with electric leads formed thereon is provided. An insulating layer is formed an the leadframe and having a plurality of openings to expose portion of the electric leads. The semiconductor chip is placed upside down onto the leadframe to have the soldering flux in contact with the portion of the electric leads exposed in the openings. The solder material flows back to form conductive interconnections between the copper pillars and the portion of the electric leads exposed in the openings. The semiconductor chip is packaged with the leadframe using a mold compound.

    摘要翻译： 提供了引线框倒装芯片（FCOL）半导体封装结构及其制造方法。 提供了一种在其上形成铜柱的半导体芯片。 在铜柱上形成阻挡层。 焊料材料涂覆在阻挡层上。 一层焊剂焊接在焊料上。 提供了形成有电引线的引线框架。 绝缘层形成为引线框架并且具有多个开口以暴露电引线的部分。 半导体芯片被倒置放置在引线框架上，以使焊剂与暴露在开口中的电引线的部分接触。 焊料材料流回到铜柱和暴露在开口中的电引线部分之间的导电互连。 使用模具化合物将半导体芯片与引线框架封装。

    TESTING PROBE AND SEMICONDUCTOR TESTING FIXTURE, AND FABRICATION METHODS THEREOF
    37.
    发明申请
    TESTING PROBE AND SEMICONDUCTOR TESTING FIXTURE, AND FABRICATION METHODS THEREOF 有权
    测试探针和半导体测试仪器及其制造方法

    公开(公告)号：US20160124016A1

    公开(公告)日：2016-05-05

    申请号：US14927169

    申请日：2015-10-29

    申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD.

    发明人： LEI SHI

    IPC分类号： G01R1/067 ,  G01R3/00 ,  G01R31/28

    CPC分类号： G01R1/06722 ,  G01R1/06733 ,  G01R3/00

    摘要： Testing probe and semiconductor testing fixture, and their fabrication methods are provided. A testing probe may configure a chamber through an insulating body. A first testing pin is disposed inside the chamber of the insulating body. The first testing pin includes: a first testing terminal on one end of the first testing pin and a first connection terminal on another end of the first testing pin. An elastic member is disposed inside the chamber and attached to the first testing pin to drive an upward or downward movement of the first testing pin along the chamber. A second testing pin is disposed around an outer sidewall surface of the insulating body enclosing the first testing pin. The second testing pin includes a second testing terminal on one end of the second testing pin and a second connection terminal on another end of the second testing pin.

    摘要翻译： 提供测试探头和半导体测试夹具及其制造方法。 测试探针可以通过绝缘体来配置腔室。 第一测试销设置在绝缘体的室内。 第一测试引脚包括：第一测试引脚的一端上的第一测试端子和第一测试引脚的另一端上的第一连接端子。 弹性构件设置在室内并且附接到第一测试销以驱动第一测试销沿着室的向上或向下运动。 第二测试销围绕包围第一测试销的绝缘体的外侧壁表面设置。 第二测试引脚包括在第二测试引脚的一端上的第二测试端子和在第二测试引脚的另一端上的第二连接端子。