公开(公告)号：US20180033762A1

公开(公告)日：2018-02-01

申请号：US15729889

申请日：2017-10-11

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/00 ,  H01L23/373 ,  H01L25/10 ,  H05K3/46 ,  H01L23/48 ,  H05K3/30 ,  H01L23/367 ,  H01L23/34 ,  H01L23/538 ,  H05K3/36 ,  H01L23/433 ,  H01L23/42 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L24/32 ,  H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L23/433 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/43 ,  H01L24/45 ,  H01L24/46 ,  H01L24/82 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/2711 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/46 ,  H01L2224/80365 ,  H01L2224/85399 ,  H01L2224/92144 ,  H01L2225/1052 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/207 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/183 ,  H05K1/185 ,  H05K3/301 ,  H05K3/305 ,  H05K3/306 ,  H05K3/366 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2203/302 ,  Y02P70/613

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

公开(公告)号：US20170263539A1

公开(公告)日：2017-09-14

申请号：US15601735

申请日：2017-05-22

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L23/433 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

公开(公告)号：US20170077014A1

公开(公告)日：2017-03-16

申请号：US15363237

申请日：2016-11-29

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495

CPC classification number: H01L23/49568 ,  H01L23/4334 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

Abstract translation: 半导体器件模块包括电介质层，具有耦合到电介质层的第一表面的半导体器件和具有耦合到电介质层的第一表面的导电垫片。 半导体器件还包括具有耦合到半导体器件的第二表面的第一表面和导电垫片的第二表面的导电散热器。 金属化层耦合到半导体器件的第一表面和导电垫片的第一表面。 金属化层延伸穿过电介质层，并通过导电垫片和散热器与半导体器件的第二表面电连接。

公开(公告)号：US20160146556A1

公开(公告)日：2016-05-26

申请号：US14549268

申请日：2014-11-20

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Kaustubh Ravindra Nagarkar ,  Matthew Jeremiah Misner ,  Faisal Razi Ahmad

IPC: F28F21/02 ,  F28F21/06

CPC classification number: F28F21/02 ,  B22F1/0018 ,  B22F3/11 ,  B22F3/1115 ,  B22F3/1137 ,  B22F3/114 ,  B22F3/24 ,  B22F7/00 ,  B22F7/02 ,  B22F2001/0037 ,  B22F2998/10 ,  F28F13/003 ,  F28F21/00 ,  F28F21/067 ,  F28F2255/18 ,  H01L23/3733 ,  Y10T428/249955 ,  Y10T428/249958 ,  Y10T428/249978 ,  B22F3/10 ,  B22F2003/244 ,  B22F3/26 ,  B22F2007/045

Abstract: Composite foams are provided including a metal template and a conformal atomic-scale film disposed over such metal template to form a 3-dimensional interconnected structure. The metal template includes a plurality of sintered interconnects, having a plurality of first non-spherical pores, a first non-spherical porosity, and a first surface-area-to-volume ratio. The conformal atomic-scale film has a plurality of second non-spherical pores, a second non-spherical porosity, and a second surface-area-to-volume ratio approximately equal to the first surface-area-to-volume ratio. The plurality of sintered interconnects has a plurality of dendritic particles and the conformal atomic-scale film includes at least one of a layer of graphene and a layer of hexagonal boron nitride.

Abstract translation: 提供了复合泡沫，其包括设置在这种金属模板上的金属模板和保形原子级膜以形成3维互连结构。 金属模板包括具有多个第一非球形孔，多个第一非球形孔隙和第一表面积与体积比的多个烧结互连。 保形原子级膜具有多个第二非球形孔，第二非球形孔隙率和大约等于第一表面积体积比的第二表面积体积比。 多个烧结互连具有多个树枝状颗粒，并且共形原子尺度膜包括石墨烯层和六方氮化硼层中的至少一个。

公开(公告)号：US20160021788A1

公开(公告)日：2016-01-21

申请号：US14676241

申请日：2015-04-01

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Shakti Singh Chauhan ,  James Neil Johnson ,  Brian Patrick Hoden ,  Graham Charles Kirk

IPC: H05K7/20 ,  B23P15/26

CPC classification number: H05K7/20427 ,  B23P15/26 ,  H01L23/3675 ,  H01L23/3732 ,  H01L23/42 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152

Abstract: An electronic device assembly includes a heat sink coupled to an electronic device to dissipate the heat produced by the electronic device. A heat spreader is coupled between the electronic device and the heat sink to transfer heat from the electronic device to the heat sink. Furthermore, at least one of the electronic device, the heat spreader, and the heat sink is disposed with a disordered carbon coating.

Abstract translation: 电子设备组件包括耦合到电子设备的散热器以散发由电子设备产生的热量。 散热器耦合在电子设备和散热器之间，以将热量从电子设备传递到散热器。 此外，电子设备，散热器和散热器中的至少一个设置有无序的碳涂层。

公开(公告)号：US09209151B2

公开(公告)日：2015-12-08

申请号：US14037728

申请日：2013-09-26

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/538 ,  H05K1/18 ,  H01L23/34 ,  H05K3/46 ,  H05K1/02 ,  H05K3/30

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

Abstract translation: 封装结构包括介电层，至少一个连接到电介质层的半导体器件，一个或多个施加到电介质层的电介质片和半导体器件，以将半导体器件嵌入其中，并且多个 形成在形成在电介质层和一个或多个电介质层中的至少一个中的半导体器件上的通孔。 封装结构还包括形成在通孔中的金属互连和在封装结构的一个或多个向外表面上以形成与半导体器件的电互连的金属互连。 电介质层由在层压过程中不流动的材料组成，并且所述一个或多个电介质片中的每一个由可固化材料构成，所述可固化材料构造成在层压过程中固化时熔化和流动，以便填充任何空气 半导体器件周围的间隙。

公开(公告)号：US20150116940A1

公开(公告)日：2015-04-30

申请号：US14068697

申请日：2013-10-31

Applicant: General Electric Company

Inventor： Joo Han Kim ,  Hendrik Pieter Jacobus de Bock ,  Jay Todd Labhart ,  Shakti Singh Chauhan ,  Graham Charles Kirk ,  Stuart Connolly

IPC: H05K1/02

CPC classification number: H05K1/0203 ,  H05K7/1461 ,  H05K7/20672 ,  Y10T29/49002

Abstract: A circuit card assembly is provided. The circuit card assembly includes a printed circuit board, at least one electronic component mounted on the printed circuit board, and a frame coupled to the printed circuit board such that the electronic component is disposed between the printed circuit board and the frame. The circuit card assembly also includes a heat transfer device coupled to the frame. The heat transfer device has a heat pipe disposed at least in part between the frame and the printed circuit board. The circuit card assembly further includes a pivotable brace biasing the heat pipe toward the electronic component to facilitate cooling the electronic component.

Abstract translation: 提供电路卡组件。 电路卡组件包括印刷电路板，安装在印刷电路板上的至少一个电子部件和耦合到印刷电路板的框架，使得电子部件设置在印刷电路板和框架之间。 电路卡组件还包括耦合到框架的传热装置。 传热装置具有至少部分地设置在框架和印刷电路板之间的热管。 电路卡组件还包括将热管朝向电子部件偏置的可枢转支架，以便于冷却电子部件。

公开(公告)号：US20150108513A1

公开(公告)日：2015-04-23

申请号：US14579569

申请日：2014-12-22

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Donald Paul Cunningham ,  Shakti Singh Chauhan

IPC: H01L33/62 ,  H01L33/00 ,  H01L33/60 ,  H01L27/15 ,  H01L33/64

CPC classification number: H05K1/189 ,  H01L25/0753 ,  H01L27/15 ,  H01L33/005 ,  H01L33/60 ,  H01L33/62 ,  H01L33/64 ,  H01L33/642 ,  H01L33/647 ,  H01L2224/24 ,  H01L2933/0066 ,  H01L2933/0075 ,  H05K1/021 ,  H05K2201/10106

Abstract: A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.

Abstract translation: 公开了一种用于封装发光半导体（LES）的系统和方法。 提供了一种LES装置，其包括散热器和安装在散热器上并电连接到其上的LES芯片阵列，每个LES芯片包括连接焊盘和配置为响应于接收的电力从其发射光的发光区域。 LES装置还包括位于每个LES芯片上并电连接到每个LES芯片以提供LES芯片阵列的控制操作的柔性互连结构，其中柔性互连结构还包括被配置为符合散热器形状的柔性介电膜 以及金属互连结构，其形成在柔性电介质膜上并且延伸穿过形成在柔性电介质膜中的通孔，以便电连接到LES芯片的连接焊盘。