公开(公告)号：US09584889B2

公开(公告)日：2017-02-28

申请号：US14011566

申请日：2013-08-27

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Edward Fuergut ,  Alfons Dehe

IPC: H01L29/84 ,  H04R1/02 ,  H04R19/00 ,  H04R31/00 ,  H04R1/08

CPC classification number: H04R1/021 ,  H04R1/086 ,  H04R19/005 ,  H04R31/006 ,  H04R2201/003 ,  H04R2201/02 ,  H04R2231/003

Abstract: A packaged MEMS device may include an embedding arrangement, a MEMS device disposed in the embedding arrangement, a sound port disposed in the embedding arrangement and acoustically coupled to the MEMS device, and a grille within the sound port. Some embodiments relate to a sound transducer component including an embedding material and a substrate-stripped MEMS die embedded into the embedding material. The MEMS die may include a diaphragm for sound transduction. The sound transducer component may further include a sound port within the embedding material in fluidic or acoustic contact with the diaphragm. Further embodiments relate to a method for packaging a MEMS device or to a method for manufacturing a sound transducer component.

Abstract translation: 封装的MEMS器件可以包括嵌入布置，布置在嵌入布置中的MEMS器件，布置在嵌入布置中并声耦合到MEMS器件的声音端口和声音端口内的格栅。 一些实施例涉及包括嵌入材料和嵌入到嵌入材料中的剥离衬底的MEMS芯片的声音传感器部件。 MEMS管芯可以包括用于声音传导的隔膜。 声音传感器组件还可以包括与隔膜流体或声学接触的嵌入材料内的声音端口。 另外的实施例涉及用于封装MEMS装置的方法或用于制造声换能器部件的方法。

公开(公告)号：US20160358886A1

公开(公告)日：2016-12-08

申请号：US15171364

申请日：2016-06-02

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Edward Fuergut ,  Joachim Mahler

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L23/44 ,  H01L23/13 ,  H01L23/5385 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/071 ,  H01L2224/291 ,  H01L2224/32227 ,  H01L2224/3701 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40228 ,  H01L2224/40499 ,  H01L2224/41051 ,  H01L2224/4118 ,  H01L2224/831 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/848 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/9201 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/15151 ,  H01L2924/15153 ,  H05K7/023 ,  H05K7/08 ,  H05K7/10 ,  H05K7/20 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83

Abstract: A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power arrangement further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.

Abstract translation: 半导体功率装置包括具有第一表面和与第一表面相对的第二表面的芯片载体。 半导体功率布置还包括附接到芯片载体的多个功率半导体芯片，其中功率半导体芯片倾斜于芯片载体的第一和/或第二表面。

公开(公告)号：US20160126211A1

公开(公告)日：2016-05-05

申请号：US14926258

申请日：2015-10-29

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Edward Fuergut ,  Horst Groeninger ,  Juergen Hoegerl

IPC: H01L23/00

CPC classification number: H01L24/72 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/433 ,  H01L24/83 ,  H01L29/7393 ,  H01L2924/351

Abstract: A semiconductor assembly is described. In accordance with one example of the invention, the semiconductor assembly comprises a semiconductor body, a top main electrode arranged on a top side, a bottom main electrode arranged on an underside, and a control electrode arranged on the top side. The semiconductor assembly further includes a spring element for the pressure contacting of the control electrode with a pressure force generated by the spring element.

Abstract translation: 描述半导体组件。 根据本发明的一个示例，半导体组件包括半导体主体，布置在顶侧的顶部主电极，设置在下侧的底部主电极和布置在顶侧的控制电极。 半导体组件还包括用于使控制电极与弹簧元件产生的压力的压力接触的弹簧元件。

公开(公告)号：US20160064255A1

公开(公告)日：2016-03-03

申请号：US14935510

申请日：2015-11-09

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess ,  Bernd Roemer ,  Edward Fuergut

IPC: H01L21/56

CPC classification number: H01L21/565 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/495 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099

Abstract: A method for manufacturing a chip arrangement, including disposing a chip over a carrier, wherein the bottom side of the chip is electrically connected to the first carrier side via one or more contact pads on the chip bottom side, disposing a first encapsulation material over the first carrier side, wherein the first encapsulation material at least partially surrounds the chip, and disposing a second encapsulation material over a second carrier side, wherein the second encapsulation material is in direct contact with the second carrier side.

Abstract translation: 一种用于制造芯片布置的方法，包括在载体上布置芯片，其中芯片的底侧通过芯片底侧上的一个或多个接触焊盘电连接到第一载体侧，在第一封装材料上设置第一封装材料 第一载体侧，其中第一封装材料至少部分地围绕芯片，并且在第二载体侧上设置第二封装材料，其中第二封装材料与第二载体侧直接接触。

公开(公告)号：US09041226B2

公开(公告)日：2015-05-26

申请号：US13798141

申请日：2013-03-13

Applicant: Infineon Technologies AG

Inventor： Rainer Steiner ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg ,  Joachim Mahler

IPC: H01L23/48 ,  H01L21/00 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/24246 ,  H01L2224/2518 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/07802 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.

Abstract translation: 在各种实施例中，提供了芯片布置。 芯片布置可以包括芯片载体和安装在芯片载体上的芯片。 芯片可以包括至少两个芯片触点和芯片与芯片载体之间的绝缘粘合剂，以将芯片粘附到芯片载体上。 所述至少两个芯片触点可以电耦合到芯片载体。

公开(公告)号：US20150108666A1

公开(公告)日：2015-04-23

申请号：US14058213

申请日：2013-10-18

Applicant: Infineon Technologies AG

Inventor： Manfred ENGELHARDT ,  Edward Fuergut ,  Hannes Eder

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/28 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/76259 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3185 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop.

Abstract translation: 一种形成薄化的封装芯片结构的方法，其中所述方法包括提供布置在电子芯片内的分离结构，通过封装结构封装电子芯片的一部分，并且选择性地稀释由封装结构部分封装的电子芯片，使得 封装结构的厚度比薄的电子芯片保持更大的厚度，其中分离结构用作减薄停止。

公开(公告)号：US20150091183A1

公开(公告)日：2015-04-02

申请号：US14042750

申请日：2013-10-01

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn ,  Edward Fuergut

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a die including at least one electronic component and a first terminal on a first side of the die and a second terminal on a second side of the die opposite the first side, wherein the first side being the main processing side of the die, and the die further including at least a third terminal on the second side; a first electrically conductive structure providing current flow from the third terminal on second side of the die to the first side through the die; a second electrically conductive structure on the first side of the die laterally coupling the second terminal with the first electrically conductive structure; and an encapsulation material disposed at least over the first side of the die covering the first terminal and the second electrically conductive structure.

Abstract translation: 提供了一种安排。 该装置可以包括：模具，其包括至少一个电子部件和在模具的第一侧上的第一端子，以及在模具的与第一侧相对的第二侧上的第二端子，其中第一侧是主要处理侧 所述管芯和所述管芯还包括在所述第二侧上的至少第三端子; 第一导电结构，其提供从模具的第二侧上的第三端子到通过模具的第一侧的电流; 在所述模具的第一侧上的第二导电结构将所述第二端子与所述第一导电结构横向地联接; 以及封装材料，其至少设置在覆盖所述第一端子和所述第二导电结构的所述管芯的所述第一侧的上方。

公开(公告)号：US20150054159A1

公开(公告)日：2015-02-26

申请号：US13974583

申请日：2013-08-23

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl ,  Edward Fuergut ,  Gottfried Beer ,  Olaf Hohlfeld

IPC: H01L23/522 ,  H01L23/28 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/561 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/24 ,  H01L24/29 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/89 ,  H01L24/92 ,  H01L25/18 ,  H01L27/12 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2413 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014

Abstract: The semiconductor module includes a carrier, a plurality of semiconductor transistor chips disposed on the carrier, a plurality of semiconductor diode chips disposed on the carrier, an encapsulation layer disposed above the semiconductor transistor chips and the semiconductor diode chips, and a metallization layer disposed above the encapsulation layer. The metallization layer includes a plurality of metallic areas forming electrical connections between selected ones of the semiconductor transistor chips and the semiconductor diode chips.

Abstract translation: 半导体模块包括载体，设置在载体上的多个半导体晶体管芯片，设置在载体上的多个半导体二极管芯片，设置在半导体晶体管芯片和半导体二极管芯片上方的封装层以及设置在半导体二极管芯片上方的金属化层 封装层。 金属化层包括形成半导体晶体管芯片中选定的半导体晶体管芯片和半导体二极管芯片之间的电连接的多个金属区域。

公开(公告)号：US08901739B2

公开(公告)日：2014-12-02

申请号：US13705367

申请日：2012-12-05

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Horst Theuss ,  Walter Diez

IPC: H01L23/488 ,  H01L29/84 ,  H01L21/56 ,  H01L21/67 ,  H01L23/48

CPC classification number: H01L23/488 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/67242 ,  H01L23/48 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L29/84 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/82

Abstract: An embedded chip package is provided. The embedded chip package includes a plurality of chips; encapsulation material embedding the plurality of chips; at least one electrical redistribution layer electrically connected to the plurality of chips; and a common terminal connected to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal.

Abstract translation: 提供嵌入式芯片封装。 嵌入式芯片封装包括多个芯片; 封装材料嵌入多个芯片; 电连接到所述多个芯片的至少一个电再分配层; 以及连接到所述至少一个电再分配层的公共终端，其中所述公共终端为所述多个芯片和所述公共终端之间的公共电信号的发射和接收中的至少一个提供接口。

公开(公告)号：US20140306356A1

公开(公告)日：2014-10-16

申请号：US13860679

申请日：2013-04-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Michael Ledutke ,  Edward Fuergut

IPC: H01L23/31 ,  H01L21/66

CPC classification number: H01L23/3107 ,  H01L21/561 ,  H01L21/67336 ,  H01L22/10 ,  H01L22/32 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess.

Abstract translation: 在各种实施例中，提供了一种布置。 该布置可以包括多个芯片; 承载所述多个芯片的芯片载体，所述芯片载体包括芯片载体缺口; 以及封装芯片载体并填充芯片载体凹口的封装材料; 其中所述封装材料的外周没有凹部。