公开(公告)号：US10403506B2

公开(公告)日：2019-09-03

申请号：US15863954

申请日：2018-01-07

Applicant: Infineon Technologies AG

Inventor： Christoph Kamseder ,  Franco Mariani ,  Andreas Bauer ,  Thomas Fischer

IPC: H01L21/304 ,  H01L21/78 ,  H01L21/67 ,  H01L21/66

Abstract: A method of manufacturing electronic dies by separating a wafer into electronic dies, wherein the method comprises forming a groove in the wafer with a first material removal tool having a first thickness, enlarging the groove by a second material removal tool having a second thickness larger than the first thickness, and subsequently increasing a depth of the groove by a third material removal tool having a third thickness smaller than the second thickness until the wafer is separated.

公开(公告)号：US20190214299A1

公开(公告)日：2019-07-11

申请号：US15863954

申请日：2018-01-07

Applicant: Infineon Technologies AG

Inventor： Christoph Kamseder ,  Franco Mariani ,  Andreas Bauer ,  Thomas Fischer

IPC: H01L21/78 ,  H01L21/67

CPC classification number: H01L21/3043 ,  B28D5/022 ,  H01L21/67092 ,  H01L21/78 ,  H01L22/34

Abstract: A method of manufacturing electronic dies by separating a wafer into electronic dies, wherein the method comprises forming a groove in the wafer with a first material removal tool having a first thickness, enlarging the groove by a second material removal tool having a second thickness larger than the first thickness, and subsequently increasing a depth of the groove by a third material removal tool having a third thickness smaller than the second thickness until the wafer is separated.

公开(公告)号：US09524940B2

公开(公告)日：2016-12-20

申请号：US15003820

申请日：2016-01-22

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L21/784 ,  H01L21/288 ,  H01L21/78 ,  H01L23/495 ,  H01L23/482

CPC classification number: H01L27/0248 ,  H01L21/288 ,  H01L21/7685 ,  H01L21/78 ,  H01L21/784 ,  H01L23/4827 ,  H01L23/495 ,  H01L23/522 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/98 ,  H01L2223/5446 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1037 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

公开(公告)号：US20160141256A1

公开(公告)日：2016-05-19

申请号：US15003820

申请日：2016-01-22

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn

IPC: H01L23/00 ,  H01L21/288 ,  H01L23/495 ,  H01L21/78

CPC classification number: H01L27/0248 ,  H01L21/288 ,  H01L21/7685 ,  H01L21/78 ,  H01L21/784 ,  H01L23/4827 ,  H01L23/495 ,  H01L23/522 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/98 ,  H01L2223/5446 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1037 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

公开(公告)号：US20150372073A1

公开(公告)日：2015-12-24

申请号：US14837880

申请日：2015-08-27

Applicant: Infineon Technologies AG

Inventor： Markus Menath ,  Thomas Fischer ,  Hermann Wendt

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F17/02 ,  H01F41/042 ,  H01L21/0274 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/64 ,  H01L27/08 ,  H01L2224/48095 ,  H01L2224/48137 ,  Y10T29/4902 ,  H01L2924/00014

Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.

Abstract translation: 公开了一种电子设备和电子设备的制造方法。 在一个实施例中，该方法包括在隔离层中形成开口，各向同性地蚀刻开口，从而形成具有弯曲侧壁的延伸开口，并在开口中形成导电材料。

公开(公告)号：US20150069591A1

公开(公告)日：2015-03-12

申请号：US14023493

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L27/0248 ,  H01L21/288 ,  H01L21/7685 ,  H01L21/78 ,  H01L21/784 ,  H01L23/4827 ,  H01L23/495 ,  H01L23/522 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/98 ,  H01L2223/5446 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1037 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

Abstract translation: 根据各种实施例，半导体器件的制造方法可以包括提供半导体工件，其包括在半导体工件的第一侧的器件区域，其中半导体工件的机械稳定性不足以抵抗至少一个后端工艺，而没有 损坏，并且在半导体工件的与半导体工件的第一侧相对的第二侧上沉积至少一个导电层，其中至少一个导电层增加半导体工件的机械稳定性，以足以抵抗至少一个 后端程序无损坏。

公开(公告)号：US20140357055A1

公开(公告)日：2014-12-04

申请号：US13903013

申请日：2013-05-28

Applicant: Infineon Technologies AG

Inventor： Anja Gissibl ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/306 ,  H01L21/78 ,  H01L21/3065

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

Abstract translation: 提供了一种用于处理半导体工件的方法，其可以包括：提供包括设置在半导体工件侧面的金属化层堆叠的半导体工件，金属化层堆叠包括至少第一层和设置在第一层上的第二层 层，其中所述第一层包含第一材料，并且所述第二层包含不同于所述第一材料的第二材料; 图案化金属化层堆叠，其中图案化金属化层堆叠包括通过蚀刻溶液湿法蚀刻第一层和第二层，蚀刻溶液对于第一材料和第二材料具有至少基本上相同的蚀刻速率。

公开(公告)号：US10153266B2

公开(公告)日：2018-12-11

申请号：US15272439

申请日：2016-09-22

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn

IPC: H01L23/48 ,  H01L27/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L21/784 ,  H01L21/288 ,  H01L21/78 ,  H01L23/495 ,  H01L23/544 ,  H01L23/482

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

公开(公告)号：US20150221523A1

公开(公告)日：2015-08-06

申请号：US14598288

申请日：2015-01-16

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/3213 ,  H01L21/283 ,  H01L27/02 ,  H01L21/306 ,  H01L23/498 ,  H01L21/56 ,  H01L21/304

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

Abstract translation: 提供了一种安排。 该布置可以包括：具有前侧和后侧的基板，基板内的管芯区域，限定管芯区域的背面的多用途层以及设置在多用途层之间的蚀刻停止层， 多用途层和背面。 多用途层可以由欧姆材料形成，并且蚀刻停止层可以是第一掺杂浓度的第一导电类型。

公开(公告)号：US20150194398A1

公开(公告)日：2015-07-09

申请号：US14662944

申请日：2015-03-19

Applicant: Infineon Technologies AG

Inventor： Roland Hampp ,  Thomas Fischer ,  Uwe Hoeckele

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L24/03 ,  H01L21/02068 ,  H01L21/02071 ,  H01L21/76837 ,  H01L21/76838 ,  H01L22/32 ,  H01L23/498 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06505 ,  H01L2224/06515 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0428 ,  H01L2924/0518 ,  H01L2924/0529 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

Abstract translation: 公开了半导体器件和方法。 半导体器件包括具有第一区域和第二区域的衬底以及布置在衬底上的绝缘层。 第一导电层布置在第一区域中的绝缘层中或绝缘层中，并且第二导电层布置在第二区域中的绝缘层中或其上。 第一导电层包括第一导电材料，第二导电层包括第二导电材料，其中第一导电材料不同于第二导电材料。 金属层布置在第一导电层上。