公开(公告)号：US08987079B2

公开(公告)日：2015-03-24

申请号：US13683344

申请日：2012-11-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L21/8234 ,  H01L21/4763 ,  H01L21/822 ,  H01L21/683 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/525 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/115 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L23/367 ,  H01L23/48

CPC classification number: H01L21/8221 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00015 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method for developing a custom device, the method including: programming a programmable device, where the programmable device includes a layer of monocrystalline first transistors and alignment marks, the first layer of monocrystalline first transistors is overlaid by interconnection layers, the interconnection layers are overlaid by a second layer of monocrystalline second transistors, where the interconnection layers include copper or aluminum, where the programming includes use of the second transistors, where the programming includes use of N type transistors and P type transistors, and where the programmable device includes at least one programmable connection; and then a step of producing a volume device according to a specific programmed design of the programmable device, where the volume device includes the at least one programmable connection replaced with a lithography defined connection, and where the volume device does not have the second layer.

Abstract translation: 一种用于开发定制设备的方法，所述方法包括：编程可编程设备，其中所述可编程设备包括单晶第一晶体管层和对准标记，所述第一层单晶第一晶体管由互连层覆盖，所述互连层被覆盖 通过第二层单晶第二晶体管，其中互连层包括铜或铝，其中编程包括使用第二晶体管，其中编程包括使用N型晶体管和P型晶体管，并且其中可编程器件至少包括 一个可编程连接; 然后根据可编程设备的特定编程设计产生音量设备的步骤，其中音量设备包括用光刻定义的连接替换的至少一个可编程连接，以及音量设备不具有第二层。

公开(公告)号：US08975670B2

公开(公告)日：2015-03-10

申请号：US13555152

申请日：2012-07-22

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L29/80 ,  H01L23/552 ,  H01L23/48 ,  H01L27/06

CPC classification number: H01L23/552 ,  H01L23/481 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.

Abstract translation: 一种半导体器件，包括：具有包括第一晶体管的第一层的半导体衬底; 覆盖第一层的屏蔽层; 覆盖所述屏蔽层的第二层，所述第二层包括第二晶体管; 其中所述屏蔽层是具有用于所述第一晶体管和所述第二晶体管之间的连接的多个区域的大部分连续的层，并且其中所述第二晶体管包括单晶区域。

公开(公告)号：US20150061036A1

公开(公告)日：2015-03-05

申请号：US14509288

申请日：2014-10-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L27/088 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L23/544

CPC classification number: H01L27/088 ,  G11C17/14 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8226 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/177 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; a second set of external connections overlying the second layer to connect the device to external devices; and an interconnection layer in-between the first layer and the second layer, where the interconnection layer includes copper or aluminum.

Abstract translation: 一种半导体器件，包括：第一层，包括单晶材料和第一晶体管，所述第一晶体管由第一隔离层覆盖; 包括第二晶体管并覆盖第一隔离层的第二层，第二晶体管包括单晶材料; 至少一个接触到所述第二晶体管，其中所述至少一个触点具有小于200nm的直径; 第一层的第一组外部连接，用于将设备连接到外部设备; 第二组外部连接，覆盖第二层以将设备连接到外部设备; 以及位于第一层和第二层之间的互连层，其中互连层包括铜或铝。

公开(公告)号：US08901613B2

公开(公告)日：2014-12-02

申请号：US13041405

申请日：2011-03-06

Applicant: Deepak C. Sekar ,  Zvi Or-Bach ,  Brian Cronquist

Inventor： Deepak C. Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/10 ,  H01L23/367

CPC classification number: H01L23/367 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor device comprising power distribution wires wherein; a portion of said wires have thermal connection to the semiconductor layer and said thermal connection designed to conduct heat but to not conduct electricity.

Abstract translation: 一种包括配电线的半导体器件， 所述导线的一部分具有与半导体层的热连接，并且所述热连接被设计为传导热量但不导电。

公开(公告)号：US08823122B2

公开(公告)日：2014-09-02

申请号：US13422057

申请日：2012-03-16

Applicant: Zvi Or-Bach ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L31/0352 ,  H01L31/18 ,  H01L25/075 ,  H01L31/0725 ,  H01L33/00 ,  H01L27/15 ,  H01L33/34

CPC classification number: H01L27/14605 ,  H01L21/8221 ,  H01L25/0756 ,  H01L27/14612 ,  H01L27/14634 ,  H01L27/153 ,  H01L31/0725 ,  H01L31/1892 ,  H01L33/0079 ,  H01L33/34 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

Abstract: An integrated device, the device including a first crystalline layer covered by an oxide layer, a second crystalline layer overlying the oxide layer, wherein the first and second crystalline layers are image sensor layers, and the device includes a third crystalline layer, wherein the third crystalline layer includes single crystal transistors.

Abstract translation: 一种集成器件，该器件包括由氧化物层覆盖的第一晶体层，覆盖氧化物层的第二晶体层，其中第一和第二晶体层是图像传感器层，并且该器件包括第三晶体层，其中第三晶体层 晶体层包括单晶晶体管。

公开(公告)号：US08709880B2

公开(公告)日：2014-04-29

申请号：US13314435

申请日：2011-12-08

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L21/82 ,  H01L21/8226 ,  H01L21/822 ,  H01L25/18 ,  H01L27/06

CPC classification number: H01L27/088 ,  G11C17/14 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8226 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/177 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of manufacturing semiconductor devices: providing a first device including a first die and second die, where the first die is diced from a first wafer, the second die is diced from a second wafer, the first die is connected to the second die using at least one through-silicon-via; providing a second device including a third die and fourth die, where the third die is diced from a third wafer, the fourth die is diced from a fourth wafer, the third die is connected to the fourth die using at least one through-silicon-via; where the first die includes a first functionality and the third die includes a second functionality, the first functionality is different than the second functionality, a majority of the masks used for processing the first wafer and the third wafer are the same; and the second die size is substantially different than the fourth die size.

Abstract translation: 一种制造半导体器件的方法：提供包括第一晶粒和第二晶粒的第一器件，其中第一晶粒从第一晶片切割，第二晶粒从第二晶片切割，第一晶粒使用 至少一个穿硅通孔; 提供包括第三管芯和第四管芯的第二器件，其中第三管芯从第三晶片切割，第四管芯从第四晶片切割，第三管芯使用至少一个穿硅硅片连接到第四管芯， 通过; 其中第一管芯包括第一功能，第三管芯包括第二功能，第一功能不同于第二功能，用于处理第一晶片和第三晶片的大多数掩模是相同的; 并且第二管芯尺寸基本上不同于第四管芯尺寸。

公开(公告)号：US08581349B1

公开(公告)日：2013-11-12

申请号：US13099010

申请日：2011-05-02

Applicant: Deepak C. Sekar ,  Zvi Or-Bach ,  Brian Cronquist

Inventor： Deepak C. Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L29/78 ,  H01L23/535

CPC classification number: H01L21/6835 ,  H01L21/84 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/10826 ,  H01L27/1108 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1203 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/785 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12032 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A 3D memory device, including: a first memory layer including a first memory transistor with side gates; a second memory layer including a second memory transistor with side gates; and a periphery circuits layer including logic transistors for controlling the memory, the periphery circuits are covered by a first isolation layer, where the first memory layer includes a first monolithically mono-crystal layer directly bonded to a second isolation layer, and the second memory layer includes a second monolithically mono-crystal layer directly bonded to the second isolation layer, and the first mono-crystal layer is bonded on top of the first isolation layer, and the second memory transistor is self-aligned to the first memory transistor.

Abstract translation: 一种3D存储器件，包括：第一存储层，包括具有侧栅极的第一存储晶体管; 第二存储层，包括具有侧栅极的第二存储晶体管; 以及包括用于控制存储器的逻辑晶体管的外围电路层，外围电路被第一隔离层覆盖，其中第一存储层包括直接接合到第二隔离层的第一单片单晶层，第二存储层 包括直接接合到第二隔离层的第二单晶单晶层，并且第一单晶层接合在第一隔离层的顶部，并且第二存储晶体管与第一存储晶体管自对准。

公开(公告)号：US20130193488A1

公开(公告)日：2013-08-01

申请号：US13683500

申请日：2012-11-21

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/08

CPC classification number: H01L27/08 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/80001

Abstract: A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer overlying the at least one metal layer; wherein the second layer includes second transistors, the second transistors include mono-crystal, the second transistors include P type transistors and N type transistors, and the second transistors are aligned to the first alignment mark with less than 40 nm alignment error.

Abstract translation: 一种半导体器件，包括：第一单晶层，包括第一晶体管，第一对准标记和至少一个金属层，所述至少一个金属层覆盖在所述第一单晶层上，其中所述至少一个金属层包括铜或铝; 以及覆盖所述至少一个金属层的第二层; 其中所述第二层包括第二晶体管，所述第二晶体管包括单晶，所述第二晶体管包括P型晶体管和N型晶体管，并且所述第二晶体管与所述第一对准标记对准，具有小于40nm的对准误差。

公开(公告)号：US20130122672A1

公开(公告)日：2013-05-16

申请号：US13635436

申请日：2011-06-28

Applicant: Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Ze'ev Wurman

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Ze'ev Wurman

IPC: H01L21/822 ,  H01L21/8238

CPC classification number: H01L21/8221 ,  G11C16/0483 ,  G11C17/06 ,  G11C17/14 ,  G11C29/82 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/845 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/5286 ,  H01L23/535 ,  H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/17764 ,  H03K19/17796 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including: implanting to form a doped layer within a second wafer; forming a second mono-crystalline layer on top of the first wafer by transferring at least a portion of the doped layer using layer transfer step, and completing the formation of second transistors on the second mono-crystalline layer including a step of forming a gate dielectric followed by second transistors gate formation step, wherein the second transistors are horizontally oriented.

Abstract translation: 一种用于形成包括第一晶片的半导体器件的方法，所述第一晶片包括包括第一晶体管和第一对准标记的第一单晶层，所述方法包括：注入以在第二晶片内形成掺杂层; 通过使用层转移步骤转移至少一部分掺杂层，在第一晶片的顶部上形成第二单晶层，并且在第二单晶层上完成第二晶体管的形成，包括形成栅极电介质的步骤 随后是第二晶体管栅极形成步骤，其中第二晶体管是水平取向的。

公开(公告)号：US08362482B2

公开(公告)日：2013-01-29

申请号：US13016313

申请日：2011-01-28

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Paul Lim

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Paul Lim

IPC: H01L21/00 ,  H01L29/10 ,  H01L33/00 ,  H01L21/70

CPC classification number: H01L21/8221 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00015 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device including a first layer including first transistors, wherein first logic circuits are constructed by the first transistors, and wherein the first logic circuits include at least one of Inverter, NAND gate, or NOR gate; and a second layer overlaying said first layer, the second layer including second transistors, wherein second logic circuits are constructed by the second transistors; wherein each logic circuit in the first logic circuits has inputs and at least one first output, the inputs are connected to the second logic circuits; wherein each logic circuit in the second logic circuits has a second output, and wherein the first transistors include first selectors adapted to selectively replace at least one of the at least one first outputs with at least one of the second outputs.

Abstract translation: 一种半导体器件，包括包括第一晶体管的第一层，其中第一逻辑电路由第一晶体管构成，并且其中第一逻辑电路包括反相器，非门或或非门中的至少一个; 以及覆盖所述第一层的第二层，所述第二层包括第二晶体管，其中第二逻辑电路由第二晶体管构成; 其中所述第一逻辑电路中的每个逻辑电路具有输入和至少一个第一输出，所述输入连接到所述第二逻辑电路; 其中所述第二逻辑电路中的每个逻辑电路具有第二输出，并且其中所述第一晶体管包括适于使用所述第二输出中的至少一个选择性地替换所述至少一个第一输出中的至少一个的第一选择器。