公开(公告)号：US09324411B2

公开(公告)日：2016-04-26

申请号：US14797057

申请日：2015-07-10

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C8/00 ,  G11C11/4096 ,  G11C11/4093 ,  G11C5/02 ,  G11C5/04 ,  H01L25/10 ,  H01L25/18 ,  H01L25/065

CPC classification number: G11C11/4093 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/4096 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US09323711B2

公开(公告)日：2016-04-26

申请号：US14682926

申请日：2015-04-09

Applicant: Rambus Inc.

Inventor： Mark A. Horowitz ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC: G06F13/42 ,  G06F13/40 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  H03K19/003 ,  H03K19/0185 ,  G11C19/00 ,  G06F13/10 ,  G06F3/06 ,  G06F13/16 ,  G06F13/364 ,  G06F12/10 ,  G11C16/32 ,  G06F12/02 ,  G11C7/22

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract translation: 集成电路装置包括具有输出驱动器的发送器电路。 集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。 集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。 集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。

公开(公告)号：US20160087819A1

公开(公告)日：2016-03-24

申请号：US14827619

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： John Wood Poulton

IPC: H04L25/03 ,  H04L25/02

CPC classification number: H04L25/03878 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0288 ,  H04L25/03343 ,  H04L2025/03808

Abstract: A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel.

Abstract translation: 一种用于提供信道均衡的发射机，其包括具有高通滤波器的第一驱动器和第二驱动器。 第一驱动器产生表示数字输入信号的第一输出信号。 第二驱动器产生表示数字输入信号的高通滤波版本的第二输出信号。 将第一和第二输出信号相加以提供信道均衡以用于在信道上传输的第三输出信号。

公开(公告)号：US20160087818A1

公开(公告)日：2016-03-24

申请号：US14865825

申请日：2015-09-25

Applicant: Rambus Inc.

Inventor： Chintan S. Thakkar ,  Kun-Yung Chang ,  Ting Wu

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03057 ,  H04L7/0045 ,  H04L7/0058 ,  H04L7/0087 ,  H04L25/03063 ,  H04L2025/03369

Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

公开(公告)号：US20160072440A1

公开(公告)日：2016-03-10

申请号：US14858965

申请日：2015-09-18

Applicant: Rambus Inc.

Inventor： Mohammad Hekmat ,  Reza Navid

IPC: H03B27/00 ,  H03L7/099

CPC classification number: H03B27/00 ,  H03L7/06 ,  H03L7/099 ,  H03L7/23

Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.

Abstract translation: 锁相环电路包括具有多个耦合振荡器的多相振荡器。 校准模块在校准过程中检测锁相环电路中的不同振荡器的频率特性之间的不匹配。 校准模块然后校准各种振荡器以补偿检测到的失配。 一旦校准，尽管不同振荡器之间的频率特性不匹配，锁相环电路可以很少或没有性能下降。

公开(公告)号：US20160071608A1

公开(公告)日：2016-03-10

申请号：US14940084

申请日：2015-11-12

Applicant: Rambus Inc.

Inventor： Gary B. Bronner ,  Brent S. Haukness ,  Mark A. Horowitz ,  Mark D. Kellam ,  Fariborz Assaderaghi

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0035 ,  G11C16/06 ,  H01L21/324

Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

Abstract translation: 存储器控制组件内的控制逻辑在相应的时间向存储器模块输出第一和第二存储器读取命令，存储器模块具有置于其上的存储器组件。 存储器控制组件内的接口电路响应于第一存储器读取命令分别经由第一多个数据路径从第一多个存储器组件同时接收第一读取数据，并且从第二个多个 所述存储器组件分别响应于所述第二存储器读取命令经由第二多个数据路径，所述第一多个存储器组件包括不包括在所述第二多个存储器组件中的至少一个存储器组件，反之亦然。

公开(公告)号：US20160056948A1

公开(公告)日：2016-02-25

申请号：US14932192

申请日：2015-11-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00

CPC classification number: H04L7/0016 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US09268071B2

公开(公告)日：2016-02-23

申请号：US14824997

申请日：2015-08-12

Applicant: Rambus Inc.

Inventor： Patrick R. Gill ,  David G. Stork

IPC: G02B5/18 ,  G02B27/00 ,  H04N5/225 ,  H04N5/232

CPC classification number: G02B5/1842 ,  G02B5/1871 ,  G02B27/0037 ,  G02B27/0068 ,  G02B27/0087 ,  H04N5/225 ,  H04N5/2254 ,  H04N5/23232 ,  H04N5/23235 ,  H04N5/23245 ,  H04N5/3696 ,  H04N9/045

Abstract: A sensing device with an odd-symmetry grating projects near-field spatial modulations onto a closely spaced photodetector array. The grating includes upper and lower features that define boundaries of odd symmetry. The features include upper and lower segments of various widths on opposite sides of each boundary, the upper segments at a height sufficient to induce one half wavelength of retardation in the band of interest relative to the lower segments. The resultant interference produces the spatial modulations for capture by the array. Photographs and other image information can be extracted from the captured data.

Abstract translation: 具有奇对称光栅的感测装置将近场空间调制投影到紧密间隔的光电检测器阵列上。 光栅包括限定奇对称边界的上部和下部特征。 这些特征包括在每个边界的相对侧上具有各种宽度的上部和下部部分，上部部分的高度足以相对于下部部分在感兴趣的带中引起一半的延迟波长。 所产生的干扰产生用于由阵列捕获的空间调制。 可以从捕获的数据中提取照片和其他图像信息。

公开(公告)号：US09264639B2

公开(公告)日：2016-02-16

申请号：US14616546

申请日：2015-02-06

Applicant: Rambus Inc.

Inventor： Michael Guidash ,  Jay Endsley ,  John Ladd ,  Thomas Vogelsang ,  Craig M. Smith

IPC: H04N5/374 ,  H04N5/365 ,  H04N5/378 ,  H04N5/376 ,  H04N5/357 ,  H01L27/146

CPC classification number: H04N5/374 ,  H01L27/14643 ,  H04N5/3577 ,  H04N5/365 ,  H04N5/3765 ,  H04N5/378

Abstract: A control pulse is generated a first control signal line coupled to a transfer gate of a pixel to enable photocharge accumulated within a photosensitive element of the pixel to be transferred to a floating diffusion node, the first control signal line having a capacitive coupling to the floating diffusion node. A feedthrough compensation pulse is generated on a second signal line of the pixel array that also has a capacitive coupling to the floating diffusion node. The feedthrough compensation pulse is generated with a pulse polarity opposite the pulse polarity of the control pulse and is timed to coincide with the control pulse such that capacitive feedthrough of the control pulse to the floating diffusion node is reduced.

Abstract translation: 生成控制脉冲，该第一控制信号线耦合到像素的传输门，以使得能够累积在该像素的光敏元件内的光电荷被传送到浮动扩散节点，该第一控制信号线具有与浮置的电容耦合 扩散节点。 在像素阵列的还具有与浮动扩散节点的电容耦合的第二信号线上产生馈通补偿脉冲。 馈通补偿脉冲以与控制脉冲的脉冲极性相反的脉冲极性产生，并被定时以与控制脉冲一致，使得控制脉冲到浮动扩散节点的电容馈通减小。

公开(公告)号：US09264055B2

公开(公告)日：2016-02-16

申请号：US14444669

申请日：2014-07-28

Applicant: Rambus Inc.

Inventor： Marko Aleksic ,  Brian S. Leibowitz

IPC: G11C11/00 ,  H03L7/099 ,  H03L7/24

CPC classification number: H03L7/24 ,  H03K5/26 ,  H03K2005/00286 ,  H03L7/081 ,  H03L7/099 ,  H03L7/0995

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract translation: 描述了具有注入锁定振荡器（ILO）的方法和装置。 在一些实施例中，国际劳工组织可以具有多个注入点和能够基于控制信号进行调整的自由运行频率。 在一些实施例中，ILO的每个注入点可以对应于相位调谐范围。 在一些实施例中，电路可以包括用于检测两个相邻相位调谐范围之间的相位边界的电路。 在一些实施例中，电路可以使用所检测的相位边界在两个相邻相位调谐范围之间切换。