公开(公告)号：US20120273941A1

公开(公告)日：2012-11-01

申请号：US13352664

申请日：2012-01-18

申请人： Zhao-Chong Zeng

发明人： Zhao-Chong Zeng

IPC分类号： H01L23/48 ,  H01L21/56

CPC分类号： H01L24/14 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00

摘要： A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses.

摘要翻译： 具有嵌入式电子部件的封装结构包括：具有穿透其中的空腔的载体; 半导体芯片，其容纳在所述空腔中并且具有设置在其上的焊料凸块; 形成在所述载体和所述半导体芯片上以封装所述焊料凸块的电介质层; 形成在电介质层上的布线层; 形成在所述电介质层和所述布线层上的绝缘保护层; 以及形成在电介质层中的焊料材料和用于电连接布线层和焊料凸块的绝缘保护层，从而缩短半导体芯片和载体之间的信号传输路径，以避免信号损失。

公开(公告)号：US08222080B2

公开(公告)日：2012-07-17

申请号：US12871447

申请日：2010-08-30

申请人： Chu-Chin Hu

发明人： Chu-Chin Hu

IPC分类号： H01L21/50

CPC分类号： H01L21/481 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/81

摘要： Provided is a fabrication method of a package structure, including cutting a full-panel packaging substrate into a plurality of packaging substrate blocks, each of which has a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate units and securing and protecting the semiconductor chips with an encapsulating material, thereby forming a plurality of packaging substrate blocks with packaging substrate units; and cutting the packaging substrate blocks to separate the packaging substrate units from each other. In the fabrication process, the alignment error between packaging substrate units in each packaging substrate block can be reduced by cutting the packaging substrate into packaging substrate blocks of appropriate size, thereby increasing the yield, and also the packaging of the semiconductor chips can be performed at the same time on all packaging substrate units in each substrate block so as to integrate fabrication of substrates with the packaging of semiconductor chips to simplify fabrication steps, thus increasing the productivity and reducing fabrication costs.

摘要翻译： 提供了一种封装结构的制造方法，包括将全面板封装基板切割成多个封装基板块，每个封装基板块具有多个封装基板单元; 在每个封装基板单元上安装和封装半导体芯片，并用封装材料固定和保护半导体芯片，由此形成具有封装基板单元的多个封装基板块; 以及切割包装衬底块以将包装衬底单元彼此分离。 在制造过程中，通过将包装基板切割成适当尺寸的封装基板块，可以减少每个封装基板块中的封装基板单元之间的对准误差，从而提高产量，并且半导体芯片的封装也可以在 同时在每个衬底块中的所有封装衬底单元上同时将衬底的制造与半导体芯片的封装相结合，以简化制造步骤，从而提高生产率并降低制造成本。

公开(公告)号：US20120097430A1

公开(公告)日：2012-04-26

申请号：US13243465

申请日：2011-09-23

申请人： Pao-Hung Chou ,  Hsien-Min Chang

发明人： Pao-Hung Chou ,  Hsien-Min Chang

IPC分类号： H05K1/02 ,  H05K3/10

CPC分类号： H01L23/49861 ,  H01L23/3121 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/181 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A packaging substrate and a method of fabricating the packaging substrate. The packaging substrate includes: a dielectric layer that has an external contact surface and an opposing chip mounting surface; a circuit layer that is embedded in the dielectric layer and exposed from the external contact surface and the chip mounting surface, the circuit layer having wire-bonding pads, conductive pads, and a circuit that electrically connects the wire-bonding pads and the conductive pads, wherein the widths of the wire-bonding pads, conductive pads, and the circuit narrow gradually from chip mounting surface to the external contact surface; and a first insulating protective layer disposed on the external contact surface of the dielectric layer and covering the dielectric layer and the circuit layer, a plurality of conductive pad openings being formed in the first insulating protective layer for exposing the conductive pads. The dielectric layer is used directly as a foundation of the packaging substrate, thereby providing advantage in miniaturization, simpler fabrication procedure, and thus low cost production.

摘要翻译： 一种封装基板及其制造方法。 封装基板包括：具有外部接触表面和相对的芯片安装表面的电介质层; 电路层，其被嵌入在所述电介质层中并且从所述外部接触表面和所述芯片安装表面露出，所述电路层具有引线接合焊盘，导电焊盘和电连接所述引线接合焊盘和所述导电焊盘的电路 其中，引线接合焊盘，导电焊盘和电路的宽度从芯片安装表面逐渐变窄到外部接触表面; 以及第一绝缘保护层，其设置在所述电介质层的所述外部接触表面上并且覆盖所述电介质层和所述电路层，在所述第一绝缘保护层中形成多个导电焊盘开口，用于暴露所述导电焊盘。 电介质层直接用作封装基板的基础，从而提供小型化，更简单的制造程序以及因此低成本生产的优点。

公开(公告)号：US20120037404A1

公开(公告)日：2012-02-16

申请号：US13208745

申请日：2011-08-12

申请人： Shih- Ping Hsu ,  Zhao-Chong Zeng

发明人： Shih- Ping Hsu ,  Zhao-Chong Zeng

IPC分类号： H05K7/20 ,  H05K1/16 ,  B23K1/19 ,  B32B38/10 ,  B23K1/00

CPC分类号： H05K3/4644 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/183 ,  H05K1/185 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4679 ,  H05K2201/0129 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

摘要： A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

摘要翻译： 包装基板包括：具有顶表面和底表面的电介质层单元; 位于所述电介质层单元的底表面中的定位焊盘; 至少一个无源元件，其具有设置在其上表面和下表面上的多个电极焊盘，所述无源元件嵌入在所述电介质层单元中并对应于所述定位焊盘; 设置在电介质层单元的顶表面上的第一电路层，第一电路层具有电连接到设置在无源元件的上表面上的电极焊盘的第一导电通孔; 以及设置在所述电介质层单元的底表面上的第二电路层，所述第二电路层具有电连接到设置在所述无源元件的下表面上的电极焊盘的第二导电通孔。 通过嵌入无源元件，整体结构可以具有减小的高度。

公开(公告)号：US20100314037A1

公开(公告)日：2010-12-16

申请号：US12780439

申请日：2010-05-14

申请人： Chin-Ming Liu

发明人： Chin-Ming Liu

IPC分类号： B32B38/10 ,  B32B38/04

CPC分类号： H01L21/6835 ,  H01L21/4857

摘要： A method for fabricating a packaging substrate includes: providing a base having a release film with two opposite surfaces, two first auxiliary dielectric layers enclosing the release film, and two metal layers disposed on the two first auxiliary dielectric layers, therewith an effective area defined on the two metal layers; forming an inner wiring layer from the two metal layers; forming on each of the two first auxiliary dielectric layers and the inner wiring layers a built-up structure having first conductive pads so as for two initial substrates to be formed on the opposite surfaces of the release film; removing whatever is otherwise lying outside the effective area; removing the release film; and forming dielectric layer openings in the two first auxiliary dielectric layers so as for two substrate bodies to be formed from the initial substrates, wherein a portion of the inner wiring layers are exposed to thereby function as second conductive pads.

摘要翻译： 一种用于制造封装衬底的方法，包括：提供具有两个相对表面的剥离膜的基底，包围隔离膜的两个第一辅助电介质层和设置在两个第一辅助介电层上的两个金属层，其中限定在 两层金属层; 从所述两个金属层形成内部布线层; 在两个第一辅助介电层和内部布线层中的每一个上形成具有第一导电焊盘的组合结构，以便形成在剥离膜的相对表面上的两个初始基板; 除去在有效区域之外的任何东西; 去除脱模膜; 以及在两个第一辅助电介质层中形成电介质层开口，以便由初始衬底形成两个衬底体，其中一部分内部配线层被暴露，从而起第二导电焊盘的作用。

公开(公告)号：US20100053920A1

公开(公告)日：2010-03-04

申请号：US12551674

申请日：2009-09-01

申请人： Zhao Chong Zeng

发明人： Zhao Chong Zeng

IPC分类号： H05K1/18 ,  H01L21/56

CPC分类号： H05K1/185 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K1/188 ,  H05K3/20 ,  H05K3/305 ,  H05K3/421 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2203/1469 ,  H05K2203/308 ,  Y10T29/49146 ,  H01L2924/00

摘要： A packaging substrate with an embedded semiconductor component and a method of fabricating the same are provided, including: fixing a semiconductor chip with electrode pads to an assisting layer with apertures through an adhesive member, wherein each of the electrode pads has a bump formed thereon, each of the apertures is filled with a filling material, and the bumps correspond to the apertures, respectively; forming a first dielectric layer on the assisting layer to encapsulate the semiconductor chip; removing the bumps and the filling material to form vias; and forming a first wiring layer on the first dielectric layer and forming first conductive vias in the vias to provide electrical connections between the electrode pads and the first wiring layer, wherein the first wiring layer comprises a plurality of conductive lands formed right on the first conductive vias, respectively.

摘要翻译： 提供了具有嵌入式半导体部件的封装基板及其制造方法，其特征在于，包括：将具有电极焊盘的半导体芯片固定在具有穿过粘合部件的孔的辅助层上，其中每个所述电极焊盘具有形成在其上的凸块， 每个孔都填充有填充材料，并且凸起分别对应于孔; 在所述辅助层上形成第一介质层以封装所述半导体芯片; 去除凸块和填充材料以形成通孔; 以及在所述第一电介质层上形成第一布线层，并且在所述通孔中形成第一导电通路以提供所述电极焊盘和所述第一布线层之间的电连接，其中所述第一布线层包括形成在所述第一导电层上的多个导电焊盘 通孔。

公开(公告)号：US20100052148A1

公开(公告)日：2010-03-04

申请号：US12541253

申请日：2009-08-14

申请人： Shih-Ping Hsu

发明人： Shih-Ping Hsu

IPC分类号： H01L23/498

CPC分类号： H05K1/112 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05111 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00014

摘要： Provided are a package structure and a package substrate, including: a substrate body having a plurality of matrix-arranged electrical contact pads formed on at least one surface thereof, wherein a solder mask layer is formed on said surface and has a plurality of openings for exposing the electrical contact pads, respectively; a first electroless-plated layer disposed on the electrical contact pads, on the walls of the openings and at the peripheries of the openings; and a second electroless-plated layer disposed on the first electroless-plated layer, the first and second electroless-plated layers constituting a recessed electrical connection structure. By forming the even electroless-plated layers on the electrical contact pads. The invention overcomes drawbacks of the prior art, namely breakage of interfaces between solder bumps and electrical contact pads and even damage of the package structure otherwise caused by excessive differences in stress between the solder bumps.

摘要翻译： 提供一种封装结构和封装基板，包括：基板主体，其具有形成在其至少一个表面上的多个矩阵布置的电接触焊盘，其中在所述表面上形成焊接掩模层，并且具有多个开口， 分别暴露电接触垫; 设置在电接触垫上，开口壁上和开口周边的第一化学镀层; 以及设置在所述第一化学镀层上的第二无电镀层，所述第一和第二无电镀层构成凹陷的电连接结构。 通过在电接触焊盘上形成均匀的无电镀层。 本发明克服了现有技术的缺点，即焊料凸块与电接触焊盘之间的界面的破坏，甚至损坏包装结构，否则由焊料凸块之间的应力过大的差异引起。

公开(公告)号：US20100006331A1

公开(公告)日：2010-01-14

申请号：US12501102

申请日：2009-07-10

申请人： Shin-Ping Hsu

发明人： Shin-Ping Hsu

IPC分类号： H05K1/16 ,  H05K1/11 ,  H05K3/30 ,  H05K3/10

CPC分类号： H05K1/185 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2924/01033 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/18162 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/10674 ,  H05K2203/1476 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A printed circuit board having a semiconductor component embedded therein and a method of fabricating the same are proposed, including: providing a circuit board body having a through hole, a first surface and an opposing second surface both provided with a core circuit layer thereon; forming on the first surface a first dielectric layer with a dielectric-layer opening for exposing part of the first surface; forming a first circuit layer on the first dielectric layer, and forming first conductive vias in the first dielectric layer; fixing in position to the through hole a semiconductor chip having an active surface with electrode pads thereon; forming in the dielectric-layer opening a third dielectric layer for covering the active surface of the semiconductor chip; forming a third circuit layer on the third dielectric layer, and forming third conductive vias in the third dielectric layer. The printed circuit board thus fabricated is warpage-free.

摘要翻译： 提出了一种嵌入其中的半导体元件的印刷电路板及其制造方法，包括：提供具有通孔的电路板主体，第一表面和相对的第二表面，其上均设有芯线电路层; 在所述第一表面上形成具有用于暴露所述第一表面的一部分的介电层开口的第一介电层; 在所述第一电介质层上形成第一电路层，以及在所述第一电介质层中形成第一导电通孔; 将具有活性表面的半导体芯片固定在通孔上，其上具有电极焊盘; 在所述电介质层开口中形成用于覆盖所述半导体芯片的有源表面的第三电介质层; 在第三电介质层上形成第三电路层，并在第三介电层中形成第三导电通孔。 这样制造的印刷电路板是无翘曲的。

公开(公告)号：US20230123068A1

公开(公告)日：2023-04-20

申请号：US17529410

申请日：2021-11-18

申请人： Unimicron Technology Corporation

发明人： Ching-Ho Hsieh ,  Ming-Hsing Wu ,  Kuei-Sheng Wu

IPC分类号： H05K1/14 ,  H05K1/02 ,  H01R12/79

摘要： A circuit board assembly is provided and includes a first circuit board, a second circuit board and a first connecting module. The first connecting module includes a first connecting wire, a first connector and a second connector. The first circuit board includes a first processor, and the second circuit board includes a second processor. One end of the first connector is connected to one end of the first connecting wire, and the other end of the first connector is connected to the first circuit board. One end of the second connector is connected to the other end of the first connecting wire, and the other end of the second connector is connected to the second circuit board. The first connector is adjacent to the first processor, and the second connector is adjacent to the second processor.

公开(公告)号：US11408799B2

公开(公告)日：2022-08-09

申请号：US17209954

申请日：2021-03-23

申请人： Unimicron Technology Corporation

发明人： Cheng-Jui Chang ,  Hung-Lin Chang

IPC分类号： G01M11/02 ,  G01B11/06

摘要： A method for measuring a thickness of a dielectric layer in a circuit board is provided. The method for measuring the thickness of the dielectric layer includes the following steps. First, a circuit board including at least one dielectric layer and at least two circuit layers is provided. The dielectric layer is between the circuit layers, and the circuit board further includes a test area including a test pattern and a through hole. The test pattern includes at least two metal layers. Next, a measuring device including a main body, at least one light source and a lens module is provided. When the main body is moved into the through hole, the light source emits light to the dielectric layer and the metal layer, and the lens module shoots the dielectric layer and the metal layer to form a captured image. The thickness of the dielectric layer is obtained via the captured image.