公开(公告)号：US20100201490A1

公开(公告)日：2010-08-12

申请号：US12404850

申请日：2009-03-16

Applicant: Chun-Hui Huang ,  Cheng-Chung Lin ,  Kuo-Yuan Tseng

Inventor： Chun-Hui Huang ,  Cheng-Chung Lin ,  Kuo-Yuan Tseng

IPC: H04B7/00

CPC classification number: G09G5/00 ,  G09G2330/02 ,  G09G2380/04

Abstract: A display device includes a RFID tag unit, a display unit, a processing unit and a power supply unit. The RFID tag unit follows a wireless communication standard of a RFID system to receive a wireless signal and outputs identification information. The processing unit electrically connected with the RFID tag unit and the display unit receives the identification information and outputs to the display unit for displaying. The power supply unit supplies operation power required to the processing unit and the display unit. The required power while the above-mentioned display device refreshes the information is supplied by the power supply unit, so that the information can be refreshed with longer communication distance and power saving is achieved. A display system including the above-mentioned display device and a reader/writer device is also disclosed.

Abstract translation: 显示装置包括RFID标签单元，显示单元，处理单元和电源单元。 RFID标签单元遵循RFID系统的无线通信标准，以接收无线信号并输出​​识别信息。 与RFID标签单元和显示单元电连接的处理单元接收识别信息并输出到显示单元以进行显示。 电源单元提供处理单元和显示单元所需的操作电源。 当上述显示装置刷新信息时所需的功率由电源单元提供，使得可以以更长的通信距离刷新信息并实现功率节省。 还公开了包括上述显示装置和读写器装置的显示系统。

公开(公告)号：US20060113616A1

公开(公告)日：2006-06-01

申请号：US11206613

申请日：2005-08-18

Applicant: Ai-Sen Liu ,  Baw-Ching Perng ,  Ming-Ta Lei ,  Yih-Shung Lin ,  Cheng-Chung Lin ,  Chia-Hui Lin

Inventor： Ai-Sen Liu ,  Baw-Ching Perng ,  Ming-Ta Lei ,  Yih-Shung Lin ,  Cheng-Chung Lin ,  Chia-Hui Lin

IPC: H01L29/94

CPC classification number: H01L21/823468 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/823456 ,  H01L29/6656

Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Abstract translation: 一种在半导体衬底上形成具有不同宽度的间隔物的方法，包括以下步骤：在衬底上设置第一间隔层，将第一间隔层限定为多个第一宽度的间隔物，并且在第 为第二间隔层预选的多个间隔物的第一间隔层，具有第二间隔层的预定数量的间隔物各自具有与第一宽度不同的第二宽度。

公开(公告)号：US07011929B2

公开(公告)日：2006-03-14

申请号：US10340245

申请日：2003-01-09

Applicant: Ming-Ta Lei ,  Yih-Shung Lin ,  Ai-Sen Liu ,  Cheng-Chung Lin ,  Baw-Ching Perng ,  Chia-Hui Lin

Inventor： Ming-Ta Lei ,  Yih-Shung Lin ,  Ai-Sen Liu ,  Cheng-Chung Lin ,  Baw-Ching Perng ,  Chia-Hui Lin

IPC: H01L21/302

CPC classification number: H01L21/823468

Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.

Abstract translation: 一种形成多个栅极侧壁间隔物的方法，每个栅极侧壁间隔件包括不同的相关栅极侧壁间隔物宽度，包括提供形成在衬底上的多个栅极结构和基本上共形地覆盖栅极结构的多个电介质层; 暴露多个的第一选定部分，然后通过各向异性蚀刻穿过包括至少最上面的介电层的厚度部分以形成第一侧壁间隔物宽度; 暴露多个的第一后续选定部分，然后蚀刻通过至少最上层介电层的厚度部分; 并且暴露多个随后的第二部分，然后通过各向异性蚀刻穿过至少最上面的介电层的厚度部分以形成随后的侧壁间隔物宽度。

公开(公告)号：USD458054S1

公开(公告)日：2002-06-04

申请号：US29149416

申请日：2001-10-11

Applicant: Cheng-Chung Lin

Designer： Cheng-Chung Lin

公开(公告)号：US08823167B2

公开(公告)日：2014-09-02

申请号：US13551421

申请日：2012-07-17

Applicant: Yi-Wen Wu ,  Cheng-Chung Lin ,  Chien Ling Hwang ,  Chung-Shi Liu

Inventor： Yi-Wen Wu ,  Cheng-Chung Lin ,  Chien Ling Hwang ,  Chung-Shi Liu

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/10145 ,  H01L2224/11002 ,  H01L2224/1112 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11827 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1317 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13551 ,  H01L2224/13561 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/1358 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13686 ,  H01L2224/13687 ,  H01L2224/13688 ,  H01L2224/1369 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3841 ,  H01L2924/0105 ,  H01L2224/11 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2224/05552

Abstract: This description relates to an integrated circuit device including a conductive pillar formed over a substrate. The conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer between the substrate and the conductive pillar. The UBM layer has a surface region. The integrated circuit device further includes a protection structure on the sidewall surface of the conductive pillar and the surface region of the UBM layer. The protection structure is formed of a non-metal material.

Abstract translation: 该描述涉及一种集成电路器件，其包括形成在衬底上的导电柱。 导电柱具有侧壁表面和顶表面。 集成电路器件还包括在衬底和导电柱之间的凸起下 - 冶金（UBM）层。 UBM层具有表面区域。 集成电路装置还包括在导电柱的侧壁表面和UBM层的表面区域上的保护结构。 保护结构由非金属材料形成。

公开(公告)号：US08104666B1

公开(公告)日：2012-01-31

申请号：US12874009

申请日：2010-09-01

Applicant: Chien Ling Hwang ,  Ying-Jui Huang ,  Cheng-Chung Lin ,  Chung-Shi Liu

Inventor： Chien Ling Hwang ,  Ying-Jui Huang ,  Cheng-Chung Lin ,  Chung-Shi Liu

IPC: B23K31/02

CPC classification number: H01L24/81 ,  B23K1/0012 ,  B23K1/203 ,  B23K3/087 ,  B23K2101/42 ,  H01L24/95 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7565 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75755 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/814 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00

Abstract: A method of bonding includes providing a first work piece, and attaching a second work piece on the first work piece, with a solder bump disposed between the first and the second work pieces. The second work piece is heated using a heating head of a heating tool to melt the solder bump. After the step of heating the second work piece, one of the first and the second work pieces is allowed to move freely in a horizontal direction to self-align the first and the second work pieces. After the step of allowing one of the first and the second work pieces to move, a temperature of the heating head is lowed until the first solder bump solidifies to form a second solder bump.

Abstract translation: 一种接合方法包括提供第一工件，并且将第二工件附接在第一工件上，其中焊料凸块设置在第一和第二工件之间。 使用加热工具的加热头加热第二工件以熔化焊料凸块。 在加热第二工件的步骤之后，允许第一工件和第二工件中的一个在水平方向上自由移动以使第一工件和第二工件自对准。 在允许第一和第二工件中的一个移动的步骤之后，加热头的温度降低直到第一焊料凸点固化以形成第二焊料凸块。

公开(公告)号：US06943077B2

公开(公告)日：2005-09-13

申请号：US10408689

申请日：2003-04-07

Applicant: Ai-Sen Liu ,  Baw-Ching Perng ,  Ming-Ta Lei ,  Yih-Shung Lin ,  Cheng-Chung Lin ,  Chia-Hui Lin

Inventor： Ai-Sen Liu ,  Baw-Ching Perng ,  Ming-Ta Lei ,  Yih-Shung Lin ,  Cheng-Chung Lin ,  Chia-Hui Lin

IPC: H01L21/02 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823468 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/823456 ,  H01L29/6656

Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Abstract translation: 一种在半导体衬底上形成具有不同宽度的间隔物的方法，包括以下步骤：在衬底上设置第一间隔层，将第一间隔层限定为多个第一宽度的间隔物，并且在第 为第二间隔层预选的多个间隔物的第一间隔层，具有第二间隔层的预定数量的间隔物各自具有与第一宽度不同的第二宽度。

公开(公告)号：US06407013B1

公开(公告)日：2002-06-18

申请号：US09761422

申请日：2001-01-16

Applicant: Lain-Jong Li ,  Tien-I Bao ,  Cheng-Chung Lin ,  Syun-Ming Jang

Inventor： Lain-Jong Li ,  Tien-I Bao ,  Cheng-Chung Lin ,  Syun-Ming Jang

IPC: H01L2131

CPC classification number: H01L21/3105 ,  H01L21/76826 ,  H01L21/76829

Abstract: Within a method for forming a dielectric layer within a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a carbon doped silicon containing dielectric layer. There is then treated the carbon doped silicon containing dielectric layer with an oxidizing plasma to form from the carbon doped silicon containing dielectric layer an oxidizing plasma treated carbon doped silicon containing dielectric layer. By treating the carbon doped silicon containing dielectric layer with the oxidizing plasma, particularly under mild conditions, to form therefrom the oxidizing plasma treated carbon doped silicon containing dielectric layer, adhesion of an additional microelectronic layer upon the oxidizing plasma treated carbon doped silicon containing dielectric layer is enhanced in comparison with adhesion of the additional microelectronic layer upon the carbon doped silicon containing dielectric layer, while not compromising dielectric properties of the carbon doped silicon containing dielectric layer.

Abstract translation: 在微电子制造中形成电介质层的方法中，首先提供衬底。 然后在衬底上形成含碳掺杂的含硅电介质层。 然后用具有氧化等离子体的碳掺杂的含硅介电层处理从含碳掺杂的含硅介电层形成氧化等离子体处理的含碳的含硅介电层。 通过用氧化等离子体处理含碳掺杂的含硅电介质层，特别是在温和条件下由其形成氧化等离子体处理的含碳硅的介电层，附加的微电子层与氧化等离子体处理的碳掺杂的含硅介电层 与附加的微电子层对含碳的含硅介电层的粘附性相比增强，同时不损害含碳掺杂的含硅介电层的介电性质。

公开(公告)号：US06372661B1

公开(公告)日：2002-04-16

申请号：US09617011

申请日：2000-07-14

Applicant: Cheng Chung Lin ,  Shwang Ming Jeng ,  Lain Jong Li

Inventor： Cheng Chung Lin ,  Shwang Ming Jeng ,  Lain Jong Li

IPC: H01L2131

CPC classification number: H01L21/02126 ,  C23C16/30 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31633 ,  H01L21/76807 ,  H01L24/05 ,  H01L2924/14 ,  Y10S438/954 ,  H01L2924/00

Abstract: A method of fabricating a CVD low-k SiOCN material. The first embodiment comprising the following steps. MeSiH3, N2O, and N2 are reacted at a molar ratio of from about 1:5:10 to 1:10:15, at a plasma power from about 0 to 400 W to deposit a final deposited film. The final deposited film is treated to stabilize the final deposited film to form a CVD low-k SiOCN material. The second embodiment comprising the following steps. A starting mixture of MeSiH3, SiH4, N2O, and N2 is reacted at a molar ratio of from about 1:1:5:10 to 1:5:10:15, in a plasma in a helium carrier gas at a plasma power from about 0 to 400 W to deposit a CVD low-k SiOCN material.

Abstract translation: 一种制造CVD低k SiOCN材料的方法。 第一实施例包括以下步骤。 MeSiH 3，N 2 O和N 2以约1:5:10至1:10:15的摩尔比以约0-400W的等离子体功率反应，沉积最后的沉积膜。 处理最终沉积的膜以稳定最终沉积膜以形成CVD低k SiOCN材料。 第二实施例包括以下步骤。 在氦载气中的等离子体中以等离子体功率的等离子体功率，以约1:1:5:10至1:5:10:15的摩尔比使MeSiH 3，SiH 4，N 2 O和N 2的起始混合物反应 约0至400W以沉积CVD低k SiOCN材料。