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41.发明授权Integrated circuit substrate having laser-embedded conductive patterns and method therefor 有权具有激光嵌入导电图案的集成电路基板及其方法公开(公告)号：US06930256B1
公开(公告)日：2005-08-16
申请号：US10138225
申请日：2002-05-01
CPC分类号： H01L24/73 , H01L21/4857 , H01L2224/16 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/1815 , H05K1/056 , H05K3/0032 , H05K3/0035 , H05K3/107 , H05K3/1258 , H05K3/423 , H05K7/1061 , H05K2201/09036 , H05K2201/09554 , H05K2203/0723 , Y10T29/49126 , Y10T29/4913 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： An integrated circuit substrate having laser-embedded conductive patterns provides a high-density mounting and interconnect structure for integrated circuits. Conductive patterns within channels on the substrate provide interconnects that are isolated by the channel sides. A dielectric material is injection-molded or laminated over a metal layer that is punched or etched. The metal layer can provide one or more power planes within the substrate. A laser is used to ablate channels on the surfaces of the outer dielectric layer for the conductive patterns. The conductive patterns are electroplated or paste screen-printed and an etchant-resistive material is applied. Finally, a plating material can be added to exposed surfaces of the conductive patterns. An integrated circuit die and external terminals can then be attached to the substrate, providing an integrated circuit having a high-density interconnect.
摘要翻译： 具有激光嵌入式导电图案的集成电路基板为集成电路提供高密度的安装和互连结构。 衬底上通道内的导电图案提供由通道侧隔离的互连。 电介质材料被注塑或层压在冲压或蚀刻的金属层上。 金属层可以在衬底内提供一个或多个电力平面。 激光用于消融用于导电图案的外部电介质层的表面上的通道。 导电图案被电镀或糊状丝网印刷并且施加耐蚀刻材料。 最后，可以将电镀材料添加到导电图案的暴露表面。 然后可以将集成电路管芯和外部端子连接到衬底，从而提供具有高密度互连的集成电路。
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公开(公告)号：US06905914B1
公开(公告)日：2005-06-14
申请号：US10291050
申请日：2002-11-08
IPC分类号： H01L21/60 , H01L21/68 , H01L23/538 , H01L21/44 , H01L23/053
CPC分类号： H01L24/96 , H01L21/56 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76877 , H01L21/78 , H01L21/82 , H01L23/3157 , H01L23/481 , H01L23/5389 , H01L24/19 , H01L24/97 , H01L2221/68345 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/83132 , H01L2224/8314 , H01L2224/83192 , H01L2224/92144 , H01L2224/97 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/3011 , H01L2224/82
摘要： A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.
摘要翻译： 形成电子部件封装的方法包括将电子部件的第一表面耦合到第一介电条的第一表面，所述电子部件包括第一表面上的接合焊盘; 首先经由穿过第一介电条的孔暴露出接合焊盘; 并且用导电材料填充第一通孔，以形成电耦合到接合焊盘的第一通孔。 接合焊盘直接连接到相应的第一通孔而不使用焊料，而不需要在接合焊盘上形成焊料润湿层。
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43.发明授权Method and system for a semiconductor for device package with a die-to-packaging substrate first bond 有权用于具有管芯到封装衬底第一接合的器件封装的半导体的方法和系统公开(公告)号：US09136159B2
公开(公告)日：2015-09-15
申请号：US13678058
申请日：2012-11-15
IPC分类号： H01L21/762 , H01L23/14 , H01L21/48 , H01L21/683 , H01L23/544 , H01L23/00 , H01L23/498
CPC分类号： H01L21/76251 , H01L21/486 , H01L21/50 , H01L21/563 , H01L21/67288 , H01L21/6836 , H01L21/6838 , H01L21/68735 , H01L23/147 , H01L23/3107 , H01L23/3128 , H01L23/3142 , H01L23/3675 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/5386 , H01L23/544 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/95 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2221/68322 , H01L2223/54486 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/27622 , H01L2224/2763 , H01L2224/29011 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/81001 , H01L2224/81005 , H01L2224/81011 , H01L2224/81024 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/83101 , H01L2224/83104 , H01L2224/83192 , H01L2224/83203 , H01L2224/83855 , H01L2224/92125 , H01L2224/92225 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589 , H01L2924/12042 , H01L2924/15311 , H01L2924/16152 , H01L2924/1616 , H01L2924/16235 , H01L2924/16251 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2224/81
摘要： Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. The additional die may comprise electronic devices. The first semiconductor die may comprise an interposer die or may comprise electronic devices. The first semiconductor die may be bonded to the packaging substrate utilizing a mass reflow process or a thermal compression process. The additional die may be bonded to the first die utilizing a mass reflow process or a thermal compression process. The bonded die may be encapsulated in a mold material, which may comprise a polymer. The one or more additional die may comprise micro-bumps for coupling to the first semiconductor die.
摘要翻译： 公开了具有管芯到基板的第一接合的半导体器件封装的方法和系统，并且可以包括将第一半导体管芯接合到封装基板，在第一半导体管芯和封装基板之间施加底部填充材料， 或更多的额外管芯到第一半导体管芯。 附加的管芯可以包括电子器件。 第一半导体管芯可以包括插入器管芯，或者可以包括电子器件。 第一半导体管芯可以利用质量回流工艺或热压缩工艺结合到封装衬底上。 可以使用质量回流工艺或热压缩工艺将附加模具结合到第一模具。 粘合的模具可以包封在可以包含聚合物的模具材料中。 一个或多个附加管芯可以包括用于耦合到第一半导体管芯的微突起。
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公开(公告)号：US08872329B1
公开(公告)日：2014-10-28
申请号：US12351596
申请日：2009-01-09
IPC分类号： H01L23/12
CPC分类号： H05K3/4617 , H01L21/486 , H01L21/6835 , H01L23/16 , H01L23/48 , H01L23/49827 , H01L2221/68345 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/00014 , H05K3/0064 , H05K2203/041 , H05K2203/061 , H05K2203/0703 , H01L2224/45099 , H01L2924/014 , H01L2924/00
摘要： An extended landing pad substrate package includes a dielectric layer having an upper surface and an opposite lower surface. A lower circuit pattern is embedded in the lower surface of the dielectric layer. The lower circuit pattern includes traces having a first thickness and extended landing pads having a second thickness greater than the first thickness. Blind via apertures are formed through an upper circuit pattern embedded into the upper surface of the dielectric layer, through the dielectric layer and to the extended landing pads. The length of the blind via apertures is minimized due to the increase second thickness of the extended landing pads as compared to the first thickness of traces. Accordingly, the width of the blind via apertures at the upper surface of the dielectric layer is minimized.
摘要翻译： 延伸的着陆垫衬底封装包括具有上表面和相对的下表面的电介质层。 在电介质层的下表面嵌入较低的电路图案。 较低电路图案包括具有第一厚度的迹线和具有大于第一厚度的第二厚度的延伸着陆焊盘。 通过孔的盲孔通过嵌入电介质层的上表面的上电路图案形成，穿过电介质层和扩展的着陆焊盘。 盲孔通孔的长度由于与第一厚度的迹线相比扩大的着陆焊盘的第二厚度增加而最小化。 因此，电介质层上表面处的盲孔通孔的宽度最小化。
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45.发明授权Method and system for a semiconductor device package with a die-to-die first bond 有权具有管芯到管芯第一接合的半导体器件封装的方法和系统公开(公告)号：US08796072B2
公开(公告)日：2014-08-05
申请号：US13678012
申请日：2012-11-15
IPC分类号： H01L21/00
CPC分类号： H01L21/76251 , H01L21/486 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/6838 , H01L23/147 , H01L23/3128 , H01L23/3675 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/13 , H01L24/16 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/95 , H01L25/0652 , H01L25/0655 , H01L2224/13147 , H01L2224/13564 , H01L2224/16147 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/75705 , H01L2224/75744 , H01L2224/81011 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/83001 , H01L2224/83192 , H01L2224/83851 , H01L2224/83855 , H01L2224/92125 , H01L2225/06513 , H01L2225/06541 , H01L2924/0781 , H01L2924/12042 , H01L2924/15311 , H01L2924/16152 , H01L2924/1616 , H01L2924/18161 , H01L2924/19105 , H01L2924/3511 , H01L2924/00014 , H01L2224/16225 , H01L2924/00 , H01L2224/16145
摘要： Methods for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die. An underfill material may be applied between the semiconductor die and the interposer die, and a mold material may be applied to encapsulate the semiconductor die. The interposer die may be thinned to expose through-silicon-vias (TSVs). The bonding of the semiconductor die may comprise adhering the semiconductor die to an adhesive layer, and bonding the semiconductor die to the interposer die. The semiconductor die may comprise micro-bumps for coupling to the interposer die, wherein the bonding comprises: positioning the micro-bumps in respective wells in a layer disposed on the interposer die; and bonding the micro-bumps to the interposer die. The semiconductor die may be bonded to the interposer die utilizing a mass reflow process or a thermal compression process.
摘要翻译： 公开了具有管芯到管芯第一接合的半导体器件封装的方法，并且可以包括将包括电子器件的一个或多个半导体管芯接合到插入器管芯。 可以在半导体管芯和内插管芯之间施加底部填充材料，并且可以施加模具材料以封装半导体管芯。 内插器管芯可以变薄以暴露通过硅通孔（TSV）。 半导体管芯的接合可以包括将半导体管芯粘附到粘合剂层上，并将半导体管芯接合到插入器管芯。 半导体管芯可以包括用于耦合到插入式管芯的微型突起，其中，所述接合包括：将微型凸块定位在设置在所述插入式管芯上的层中的相应的阱中; 并将微型凸块接合到插入件模具。 半导体管芯可以利用质量回流工艺或热压缩工艺结合到插入式管芯上。
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公开(公告)号：US20140134800A1
公开(公告)日：2014-05-15
申请号：US13678026
申请日：2012-11-15
IPC分类号： H01L21/78 , H01L21/762
CPC分类号： H01L21/486 , H01L21/56 , H01L21/561 , H01L21/568 , H01L22/14 , H01L22/20 , H01L23/04 , H01L23/147 , H01L23/3675 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/95 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/73204 , H01L2224/73253 , H01L2224/81001 , H01L2224/81191 , H01L2224/81908 , H01L2224/81986 , H01L2224/83192 , H01L2224/83908 , H01L2224/83986 , H01L2224/92125 , H01L2924/12042 , H01L2924/16152 , H01L2924/1616 , H01L2924/18161 , H01L2924/19105 , H01L2924/00
摘要： Methods for temporary wafer molding for chip-on-wafer assembly may include bonding one or more semiconductor die to an interposer wafer, applying a temporary mold material to encapsulate the bonded die, and backside processing the interposer, which may be singulated to generate assemblies comprising the bonded die, the interposer die, which may be bonded to packaging substrates. The temporary mold material may be removed and the bonded die may be tested. Additional die may be bonded to the assemblies based on the electrical testing. The interposer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The backside processing may comprise thinning the interposer wafer to expose through-silicon-vias (TSVs) and placing metal contacts on the exposed TSVs. The die may be bonded to the interposer utilizing a mass reflow or thermal compression process.
摘要翻译： 用于片上晶片组装的临时晶片成型的方法可以包括将一个或多个半导体管芯接合到插入器晶片，施加临时模制材料以封装接合的管芯，以及背面处理插入件，其可以被单个化以产生组件， 可以粘合到封装衬底上的粘合模，插入模。 可以移除临时模具材料并且可以测试粘合的模具。 基于电气测试，附加模具可以结合到组件。 可以使用激光切割工艺，反应离子蚀刻，锯切技术和等离子体蚀刻工艺中的一种或多种来切割插入器。 背面处理可以包括使内插器晶片变薄以暴露穿过硅通孔（TSV）并将金属触点放置在暴露的TSV上。 可以使用质量回流或热压缩工艺将管芯结合到插入件。
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47.发明申请Method And System For A Semiconductor Device Package With A Die To Interposer Wafer First Bond 有权一种半导体器件封装的方法和系统，具有内插器晶片第一键公开(公告)号：US20140134796A1
公开(公告)日：2014-05-15
申请号：US13678046
申请日：2012-11-15
IPC分类号： H01L21/50
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/50 , H01L21/561 , H01L21/6836 , H01L21/78 , H01L23/147 , H01L23/3128 , H01L23/3135 , H01L23/3675 , H01L23/49805 , H01L23/49816 , H01L23/49838 , H01L23/5384 , H01L24/13 , H01L24/75 , H01L24/81 , H01L24/97 , H01L25/0655 , H01L25/16 , H01L25/50 , H01L27/108 , H01L2221/68381 , H01L2224/13147 , H01L2224/29011 , H01L2224/73104 , H01L2224/73204 , H01L2224/73253 , H01L2224/75704 , H01L2224/75744 , H01L2224/7598 , H01L2224/81005 , H01L2224/8114 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/83192 , H01L2224/83203 , H01L2224/83862 , H01L2224/9211 , H01L2224/97 , H01L2924/12042 , H01L2924/3511 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.
摘要翻译： 公开了具有管芯到插入件晶片第一接合的半导体器件封装的方法和系统，并且可以包括将包括电子器件的多个半导体管芯结合到插入器晶片，以及在管芯和插入器晶片之间施加底部填充材料。 可以应用模具材料来封装模具。 内插器晶片可以被薄化以暴露通过硅通孔（TSV），并且可以将金属触点施加到暴露的TSV。 内插器晶片可以被单个化以产生包括半导体管芯和插入器管芯的组件。 可以使用粘合剂膜将管芯放置在插入件晶片上。 可以使用激光切割工艺，反应离子蚀刻，锯切技术和等离子体蚀刻工艺中的一种或多种来切割插入器晶片。 可以使用质量回流或热压缩工艺将管芯结合到插入件晶片。
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公开(公告)号：US08501543B1
公开(公告)日：2013-08-06
申请号：US13472961
申请日：2012-05-16
IPC分类号： H01L21/00
CPC分类号： H01L24/96 , H01L21/56 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76877 , H01L21/78 , H01L21/82 , H01L23/3157 , H01L23/481 , H01L23/5389 , H01L24/19 , H01L24/97 , H01L2221/68345 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/83132 , H01L2224/8314 , H01L2224/83192 , H01L2224/92144 , H01L2224/97 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/3011 , H01L2224/82
摘要： A method and structure provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings, thereby avoiding the use of photoimagable materials and photo-etching processes.
摘要翻译： 一种方法和结构提供了直接写入晶片级芯片级封装（DWWLCSP），其利用永久层/涂层和直接写入技术对这些层/涂层进行图案化，从而避免使用光可塑材料和光蚀刻工艺。
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49.发明授权Semiconductor package including top-surface terminals for mounting another semiconductor package 有权半导体封装包括用于安装另一半导体封装的顶表面端子公开(公告)号：US08110909B1
公开(公告)日：2012-02-07
申请号：US12655724
申请日：2010-01-05
IPC分类号： H01L23/02
CPC分类号： H01L24/73 , H01L21/4857 , H01L2224/16 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/1815 , H05K1/056 , H05K3/0032 , H05K3/0035 , H05K3/107 , H05K3/1258 , H05K3/423 , H05K7/1061 , H05K2201/09036 , H05K2201/09554 , H05K2203/0723 , Y10T29/49126 , Y10T29/4913 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die. The vias may be plated, paste-filled, filled with a low melting point alloy and may have a conical profile for improved plating performance.
摘要翻译： 包括用于安装另一半导体封装的顶表面端子的半导体封装提供三维电路配置，其可以提供具有标准设计的现有格栅阵列封装的可移除连接。 半导体管芯安装在电连接到具有设置在底侧的端子的电路基板上，用于连接到外部系统。 封装裸片和衬底，并且将通孔激光烧蚀或以其它形式通过封装形成到衬底的顶表面上的端子，其提供可安装另一个栅格阵列半导体封装的栅格阵列安装焊盘。 通孔的底侧可以终止并电连接到基板上的端子，半导体封装的底部的端子（通过端子）或半导体管芯的顶部上的端子。 通孔可以被电镀，糊状填充，填充低熔点合金，并且可以具有锥形轮廓以改善电镀性能。
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50.发明授权Semiconductor package including top-surface terminals for mounting another semiconductor package 有权半导体封装包括用于安装另一半导体封装的顶表面端子公开(公告)号：US08026587B1
公开(公告)日：2011-09-27
申请号：US12802661
申请日：2010-06-10
IPC分类号： H01L23/22
CPC分类号： H01L24/73 , H01L21/4857 , H01L2224/16 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/1815 , H05K1/056 , H05K3/0032 , H05K3/0035 , H05K3/107 , H05K3/1258 , H05K3/423 , H05K7/1061 , H05K2201/09036 , H05K2201/09554 , H05K2203/0723 , Y10T29/49126 , Y10T29/4913 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die. The vias may be plated, paste- filled, filled with a low melting point alloy and may have a conical profile for improved plating performance.
摘要翻译： 包括用于安装另一半导体封装的顶表面端子的半导体封装提供三维电路配置，其可以提供具有标准设计的现有格栅阵列封装的可移除连接。 半导体管芯安装在电连接到具有设置在底侧的端子的电路基板上，用于连接到外部系统。 封装裸片和衬底，并且将通孔激光烧蚀或以其它形式通过封装形成到衬底的顶表面上的端子，其提供可安装另一个栅格阵列半导体封装的栅格阵列安装焊盘。 通孔的底侧可以终止并电连接到基板上的端子，半导体封装的底部的端子（通过端子）或半导体管芯的顶部上的端子。 通孔可以镀覆，糊状填充，填充低熔点合金，并且可以具有锥形轮廓以改善电镀性能。
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