公开(公告)号：US20100065949A1

公开(公告)日：2010-03-18

申请号：US12212498

申请日：2008-09-17

申请人： Andreas Thies ,  Harry Hedler ,  Roland Irsigler

发明人： Andreas Thies ,  Harry Hedler ,  Roland Irsigler

IPC分类号： H01L23/538 ,  H01L21/60

CPC分类号： H01L24/16 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/01007 ,  H01L2224/05552

摘要： Structures and methods of forming stacked chips are disclosed. In one embodiment, a first chip is disposed over a second chip, a top surface of the first and the second chip includes active circuitry. A first through substrate via is disposed within the first chip, the first through substrate via includes a protruding tip projecting below a bottom surface of the first chip, the bottom surface being opposite the top surface. A second through substrate via is disposed on the second chip, the second through substrate via including an opening, wherein the first protruding tip of the first chip is disposed within the opening of the second chip.

摘要翻译： 公开了形成堆叠芯片的结构和方法。 在一个实施例中，第一芯片设置在第二芯片上，第一芯片和第二芯片的顶表面包括有源电路。 第一穿通基板通孔设置在第一芯片内，第一通孔基板通孔包括在第一芯片的底表面下方突出的突出尖端，底表面与顶表面相对。 第二穿通基板通孔设置在第二芯片上，第二通孔基板通孔包括开口，其中第一芯片的第一突出末端设置在第二芯片的开口内。

公开(公告)号：US07545048B2

公开(公告)日：2009-06-09

申请号：US12014632

申请日：2008-01-15

申请人： Torsten Meyer ,  Harry Hedler

发明人： Torsten Meyer ,  Harry Hedler

IPC分类号： H01L23/48

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05644 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/82 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A stacked die package includes a substrate or interposer board that includes a contact area on a top surface and landing pads surrounding the contact area. Solder pads are disposed on an opposite side of the substrate. The solder pads are electrically connected with the landing pads by inner board wiring. A reconstituted die, which includes a die surrounded by a frame, is mounted over the substrate. A top die is mounted over the reconstituted die. Both the reconstituted die and the top die are electrically connected to the substrate, e.g., by wire bonds.

摘要翻译： 堆叠的管芯封装包括衬底或插入板，其包括顶表面上的接触区域和围绕接触区域的接合焊盘。 焊盘设置在基板的相对侧上。 焊盘通过内板布线与着陆焊盘电连接。 包括由框架包围的模具的重构模具安装在基板上。 顶部模具安装在重构的模具上。 重构的管芯和顶部管芯都通过例如引线接合而与衬底电连接。

公开(公告)号：US07274107B2

公开(公告)日：2007-09-25

申请号：US11038465

申请日：2005-01-21

申请人： Harry Hedler ,  Thorsten Meyer ,  Andreas Wolter

发明人： Harry Hedler ,  Thorsten Meyer ,  Andreas Wolter

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49827 ,  H01L21/50 ,  H01L23/04 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to semiconductor devices. According to the present invention a semiconductor device is described, comprising: a substrate for carrying a semiconductor chip on a first surface of said substrate; said semiconductor chip being punctually attached to said substrate on said first surface of said substrate via a single attachment point; and means for protecting said semiconductor chip on said first surface of said substrate at least protecting said semiconductor chip laterally.

摘要翻译： 本发明涉及半导体器件。 根据本发明，描述了一种半导体器件，包括：用于在所述衬底的第一表面上承载半导体芯片的衬底; 所述半导体芯片通过单个连接点准时地附接到所述基板的所述第一表面上的所述基板; 以及用于保护所述衬底的所述第一表面上的所述半导体芯片至少保护所述半导体芯片的装置。

公开(公告)号：US07247948B2

公开(公告)日：2007-07-24

申请号：US10836143

申请日：2004-04-30

申请人： Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer

发明人： Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer

IPC分类号： H01L21/82 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor substrate, at least a first and second rewiring device on a first surface of the semiconductor substrate for the provision of an electrical contact-connection of the semiconductor substrate, and a tapering, continuous opening from a first surface to a second, opposite surface of the semiconductor substrate. At least a third and fourth rewiring device is disposed on the second surface of the semiconductor substrate and a patterned metallization on the side areas of the opening for the separate contact-connection of the first and at least the second rewiring device.

摘要翻译： 半导体器件具有半导体衬底，至少第一和第二重新布线装置在半导体衬底的第一表面上，用于提供半导体衬底的电接触连接，以及从第一表面到第二表面的渐缩连续的开口 第二，半导体衬底的相对表面。 至少第三和第四重新布线装置设置在半导体衬底的第二表面上，并且在开口的侧面区域上形成图案化金属化，用于第一和第二重新布线装置的单独接触连接。

公开(公告)号：US07208345B2

公开(公告)日：2007-04-24

申请号：US11126392

申请日：2005-05-11

申请人： Thorsten Meyer ,  Harry Hedler

发明人： Thorsten Meyer ,  Harry Hedler

IPC分类号： H01L21/48 ,  H01L21/50

CPC分类号： H01L25/50 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A first reconstituted wafer is formed, followed by a first redistribution layer. In parallel, a second reconstituted wafer is formed. The second reconstituted wafer is diced along a gap such that individualized embedded chips are formed having tilted sidewalls defining an angle of more than 90 degrees with respect to the active surface of the reconstituted wafer. The embedded chips are placed with the backside on an active surface of the first reconstituted wafer on the first redistribution layer. Afterwards, a second redistribution layer is formed on the active surface of the embedded chips and tilted sidewalls wherein the second redistribution layer connects contact pads of the second chips with the first redistribution layer.

摘要翻译： 形成第一重构晶片，随后是第一再分配层。 平行地，形成第二重构晶片。 第二重构​​晶片沿着间隙被切割，使得个别化的嵌入式芯片形成为具有相对于重构的晶片的有效表面限定大于90度的角度的倾斜侧壁。 将嵌入式芯片的背面放置在第一再分配层上的第一重构晶片的有效表面上。 之后，在嵌入式芯片的有源表面和倾斜的侧壁上形成第二再分配层，其中第二再分配层将第二芯片的接触焊盘与第一再分布层连接。

公开(公告)号：US20070032059A1

公开(公告)日：2007-02-08

申请号：US11195462

申请日：2005-08-02

申请人： Harry Hedler ,  Roland Irsigler

发明人： Harry Hedler ,  Roland Irsigler

IPC分类号： H01L21/44

CPC分类号： H01L21/76898

摘要： A method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure This invention provides a method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure. The method comprises the steps of: providing a semiconductor wafer (1) having a bulk region (1a) and an active region (1b); forming a plurality of contact trenches (5a-5f) in said semiconductor wafer (1) which extend from an upper surface (O) of said active region (1b) into said bulk region (1a); forming a first dielectric isolation layer (8) on the sidewalls and the bottoms of said contact trenches (5a-5f); providing a first conductive filling (10) in said plurality of contact trenches (5a-5f); forming an aligned via (V) in said semiconductor wafer (1) which extends from a backside (B) of said bulk region (1a) into said plurality of contact trenches (5a-5f) and exposes the conductive filling (10) of said plurality of contact trenches (5a-5f); providing a second dielectric isolation layer (15) on the sidewall of said via (V); and providing a second conductive filling (20) in said via (V) which contacts the exposed conductive filling (10) of said plurality of contact trenches (5a-5f) thus forming said wafer through-contact.

摘要翻译： 一种制造具有晶片通孔接触和相应的半导体结构的半导体结构的方法本发明提供一种制造具有晶片通孔接触和相应的半导体结构的半导体结构的方法。 该方法包括以下步骤：提供具有体区（1a）和有源区（1b）的半导体晶片（1）; 在所述半导体晶片（1）中形成从所述有源区（1b）的上表面（O）延伸到所述体区（1a）中的多个接触沟槽（5a-5f）; 在所述接触沟槽（5a-5f）的侧壁和底部上形成第一介电隔离层（8）; 在所述多个接触沟槽（5a-5f）中提供第一导电填料（10）; 在所述半导体晶片（1）中形成对准的通孔（V），所述半导体晶片从所述主体区域（1a）的背面（B）延伸到所述多个接触沟槽（5a-5f）中并且暴露所述导电填料 ）所述多个接触沟槽（5a-5f）中; 在所述通孔（V）的侧壁上提供第二介电隔离层（15）; 以及在所述通孔（V）中提供与所述多个接触沟槽（5a-5f）的暴露的导电填料（10）接触从而形成所述晶片通过接触的第二导电填料（20）。

公开(公告)号：US20060220262A1

公开(公告)日：2006-10-05

申请号：US11098780

申请日：2005-04-04

申请人： Torsten Meyer ,  Harry Hedler

发明人： Torsten Meyer ,  Harry Hedler

IPC分类号： H01L23/48

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05644 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/82 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A stacked die package includes a substrate or interposer board that includes a contact area on a top surface and landing pads surrounding the contact area. Solder pads are disposed on an opposite side of the substrate. The solder pads are electrically connected with the landing pads by inner board wiring. A reconstituted die, which includes a die surrounded by a frame, is mounted over the substrate. A top die is mounted over the reconstituted die. Both the reconstituted die and the top die are electrically connected to the substrate, e.g., by wire bonds.

公开(公告)号：US07074696B1

公开(公告)日：2006-07-11

申请号：US10630632

申请日：2003-07-29

申请人： Gerd Frankowsky ,  Harry Hedler ,  Barbara Vasquez

发明人： Gerd Frankowsky ,  Harry Hedler ,  Barbara Vasquez

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/46

CPC分类号： H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599

摘要： The present invention provides a method for fabricating semiconductor circuit modules having the following steps: application of a patterned connection layer to a transfer substrate, application of active circuit devices and/or passive circuit devices with contact areas pointing toward the patterned connection layer, connection of the circuit devices to one another by means of a filler at least between the circuit devices, removal of the transfer substrate, and application of electrical connection devices for selective contact connection of the contact area of the circuit devices to one another.

摘要翻译： 本发明提供了一种制造半导体电路模块的方法，其具有以下步骤：将图案化连接层应用于转移衬底，施加有接触区域指向图案化连接层的有源电路器件和/或无源电路器件， 至少在电路装置之间通过填料相互连接的电路装置，去除转移基板以及施加用于使电路装置的接触区域彼此选择性接触连接的电连接装置。

公开(公告)号：US20060091561A1

公开(公告)日：2006-05-04

申请号：US10515613

申请日：2003-05-23

申请人： Jochen Dangelmaier ,  Harry Hedler ,  Roland Irsigler ,  Stefan Paulus

发明人： Jochen Dangelmaier ,  Harry Hedler ,  Roland Irsigler ,  Stefan Paulus

IPC分类号： H01L23/48 ,  H01L21/48

CPC分类号： H01L21/568 ,  B29C2043/5825 ,  H01L21/4846 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/8181 ,  H01L2224/83385 ,  H01L2224/85424 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01026 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/207 ,  H01L2224/05599

摘要： The invention relates to an electronic device and a method for producing it having external area contacts and having a rewiring structure and also having a semiconductor chip, which has contact areas, the external area contacts being electrically connected to the contact areas at least by means of the rewiring structure, and the external area contacts and/or the rewiring structure having chemically or galvanically selectively deposited metal.

摘要翻译： 本发明涉及一种电子器件及其制造方法，该电子器件及其制造方法具有外部区域接触并且具有重新布线结构，并且还具有具有接触区域的半导体芯片，所述外部区域触点至少借助于 重新布线结构以及具有化学或电化学选择性沉积金属的外部区域接触和/或重新布线结构。

公开(公告)号：US20060027935A1

公开(公告)日：2006-02-09

申请号：US11172083

申请日：2005-06-30

申请人： Harry Hedler ,  Simon Muff

发明人： Harry Hedler ,  Simon Muff

IPC分类号： H01L23/48

CPC分类号： H05K1/181 ,  G11C5/04 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/31 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/429 ,  H05K2201/10545 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： The present invention relates to a semiconductor device which provides a shortest possible connection between two semiconductor components 10a and 10b arranged in a manner lying opposite on a substrate 2. The two semiconductor components 10a and 10b are in each case arranged with their chip contact-connection regions 11a and 11b facing the substrate 2. A vertical through-plating device 20 connects the two chip contact-connection regions 11a and 11b.

摘要翻译： 本发明涉及一种提供以与衬底2相对的方式布置的两个半导体组件10a和10b之间的最短可能连接的半导体器件。两个半导体组件10a和10b分别以它们 芯片接触连接区域11a和11b面对基板2.垂直通镀装置20连接两个芯片接触连接区域11a和11b。