公开(公告)号：US09978748B2

公开(公告)日：2018-05-22

申请号：US14964445

申请日：2015-12-09

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Alexander Reznicek

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method is provided for forming an integrated circuit with FinFETs. Initially, a fin is received with a dummy gate passing thereover. The dummy gate is removed to form a space over the fin. A temporary layer is subsequently placed in the space, and an element from the temporary layer is caused to pass into a portion of the fin to form a modified fin portion. After the temporary layer is removed, at least part of the modified fin portion is etched away to form a gap in the fin.

公开(公告)号：US20180076040A1

公开(公告)日：2018-03-15

申请号：US15262206

申请日：2016-09-12

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Hemanth Jagannathan ,  Choonghyun Lee ,  Vijay Narayanan

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/161 ,  H01L29/51

CPC classification number: H01L21/28255 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02247 ,  H01L21/02255 ,  H01L29/161 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.

公开(公告)号：US20170278939A1

公开(公告)日：2017-09-28

申请号：US15620253

申请日：2017-06-12

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Hemanth Jagannathan ,  Koichi Motoyama ,  Oscar Van Der Straten

IPC: H01L29/45 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L29/45 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76882 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/78

Abstract: Source/drain contact structures that exhibit low contact resistance and improved electromigration properties are provided. After forming a first contact conductor portion comprising a metal having a high resistance to electromigration such as tungsten at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion comprising a highly conductive metal such as copper or a copper alloy is formed over the first contact conductor portion.

公开(公告)号：US09761655B1

公开(公告)日：2017-09-12

申请号：US15186919

申请日：2016-06-20

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Lawrence A. Clevenger ,  Hemanth Jagannathan ,  Roger A. Quon

IPC: H01L49/02 ,  H01L21/20 ,  H01L29/06 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/75 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53257 ,  H01L29/0649

Abstract: Stacked planar capacitor structures and methods of fabricating the same generally include stacking two or more capacitors with three electrodes by sharing a middle electrode, wherein each capacitor has a different area. The stacked structure does not include step heights, which permits fabrication of multiple structures where desired.

公开(公告)号：US20170229459A1

公开(公告)日：2017-08-10

申请号：US15284759

申请日：2016-10-04

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Alexander Reznicek ,  Devendra K. Sadana ,  Charan V. Surisetty

IPC: H01L27/092 ,  H01L29/267 ,  H01L29/165 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/20 ,  H01L29/08

CPC classification number: H01L27/0921 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/302 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823892 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for forming a semiconductor device comprises forming an insulator layer on a semiconductor substrate, removing portions of the insulator layer to form a first cavity and a second cavity, the first cavity exposing a first portion of the semiconductor substrate an the second cavity exposing a second portion of the semiconductor substrate, growing a first semiconductor material in the first cavity and the second cavity. Growing a second semiconductor material on the first semiconductor material in the first cavity and the second cavity, growing a third semiconductor material on the second semiconductor material in the first cavity and the second cavity. Forming a mask over the third semiconductor material in the first cavity, removing the third semiconductor material from the second cavity to expose the second semiconductor material in the second cavity, and growing a fourth semiconductor material on the second semiconductor material in the second cavity.

公开(公告)号：US09721842B2

公开(公告)日：2017-08-01

申请号：US15058309

申请日：2016-03-02

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Hemanth Jagannathan ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Rekha Rajaram

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/321 ,  H01L21/033 ,  H01L21/225 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/324 ,  H01L29/66 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/027 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L21/823462 ,  H01L21/02321 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/225 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.

公开(公告)号：US20170194459A1

公开(公告)日：2017-07-06

申请号：US14985733

申请日：2015-12-31

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Veeraraghavan S. Basker ,  Johnathan E. Faltermeier ,  Hemanth Jagannathan ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28185 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities.

公开(公告)号：US09653537B1

公开(公告)日：2017-05-16

申请号：US15275846

申请日：2016-09-26

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Paul C. Jamison

IPC: H01L29/06 ,  H01L29/41 ,  H01L29/43 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L21/28088 ,  H01L21/28556 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/47 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78642

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures for controlling a threshold voltage on a nanosheet-based transistor. A nanosheet stack is formed over a substrate. The nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A tri-layer gate metal stack is formed on each nanosheet. The tri-layer gate metal stack includes an inner nitride layer formed on a surface of each nanosheet, a doped transition metal layer formed on each inner nitride layer, and an outer nitride layer formed on each doped transition metal layer.

公开(公告)号：US20170125444A1

公开(公告)日：2017-05-04

申请号：US15408053

申请日：2017-01-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hemanth Jagannathan ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/02 ,  H01L29/04

CPC classification number: H01L27/1207 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/20

Abstract: A semiconductor-on-insulator (SOI) substrate is provided that includes a silicon or germanium handle substrate that is miscut from 2 degrees to 8 degrees towards the crystallographic direction or the crystallographic direction. The topmost semiconductor layer is removed from a portion of the SOI substrate, and then a trench having a high aspect ratio is formed within the insulator layer of the SOI substrate and along the crystallographic direction or the crystallographic direction. An III-V compound semiconductor pillar, which includes a lower portion that has a first defect density and an upper portion that has a second defect density that is less than the first defect density, is then formed in the trench.

公开(公告)号：US09627510B1

公开(公告)日：2017-04-18

申请号：US14956602

申请日：2015-12-02

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/4175 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/66553 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device comprises forming a dummy gate on a substrate; forming spacers at opposing sides of the dummy gate; depositing a sacrificial interlayer dielectric over the dummy gate; planarizing the interlayer dielectric to expose the dummy gate; removing the dummy gate; forming a replacement metal gate with a protective cap between the spacers and on the substrate to replace the removed dummy gate; removing the sacrificial interlayer dielectric; siliciding exposed areas of the substrate adjacent to the replacement metal gate; depositing a final interlayer dielectric over the replacement metal gate and the exposed silicided areas; and forming vias through the final interlayer dielectric to the silicided areas.