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公开(公告)号：US08299455B2
公开(公告)日：2012-10-30
申请号：US11872291
申请日：2007-10-15
IPC分类号： H01L29/06
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
摘要翻译： 自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。 具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。 在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。 接触电阻的降低又改善了通过结构的电流的流动。 除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。
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公开(公告)号：US08298860B2
公开(公告)日：2012-10-30
申请号：US13038467
申请日：2011-03-02
IPC分类号： H01L21/60
CPC分类号： G06F17/5068 , H01L23/3672 , H01L23/473 , H01L23/481 , H01L25/0657 , H01L27/0688 , H01L2224/16 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/12044
摘要： Bottom sides of two semiconductor substrates are brought together with at least one bonding material layer therebetween and bonded to form a bonded substrate. A cavity with two openings and a contiguous path therebetween is provided within the at least one bonding layer. At least one through substrate via and other metal interconnect structures are formed within the bonded substrate. The cavity is employed as a cooling channel through which a cooling fluid flows to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. Alternatively, a conductive cooling fin with two end portions and a contiguous path therebetween is formed within the at least one bonding layer. The two end portions of the conductive cooling fin are connected to heat sinks to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate.
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公开(公告)号：US20120193790A1
公开(公告)日：2012-08-02
申请号：US13444193
申请日：2012-04-11
申请人： Paul S. Andry , Edward C. Cooney, III , Edmund J. Sprogis , Anthony K. Stamper , Cornelia K. Tsang
发明人： Paul S. Andry , Edward C. Cooney, III , Edmund J. Sprogis , Anthony K. Stamper , Cornelia K. Tsang
IPC分类号： H01L23/498
CPC分类号： H01L24/10 , H01L23/5384 , H01L24/13 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/05686 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01327 , H01L2924/04953 , H01L2924/12044 , H01L2924/15311 , H01L2924/00 , H01L2924/00014 , H01L2924/049
摘要： A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.
摘要翻译： 电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。 使用粘合剂层将半导体衬底附接到透明手柄衬底。 半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。 减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。 半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。 照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。 然后可以将半导体中介层结合到封装衬底或半导体芯片。
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公开(公告)号：US08232139B1
公开(公告)日：2012-07-31
申请号：US13426835
申请日：2012-03-22
IPC分类号： H01L21/00
CPC分类号： H01L25/16 , H01L23/147 , H01L23/49827 , H01L23/50 , H01L23/552 , H01L23/645 , H01L24/13 , H01L24/16 , H01L2223/6661 , H01L2223/6672 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16265 , H01L2924/14 , H01L2924/1433 , H01L2924/157 , H01L2924/19011 , H01L2924/19042 , H01L2924/19103 , H01L2924/19107 , H01L2224/48091 , H01L2924/00014
摘要： Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.
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公开(公告)号：US08211728B2
公开(公告)日：2012-07-03
申请号：US12632836
申请日：2009-12-08
IPC分类号： H01L21/00
CPC分类号： H01L21/76838 , H01H59/0009
摘要： A first dielectric material layer and a second dielectric material layer are formed on a substrate. Three conductive portions are formed within the second dielectric material layer. An optional third dielectric material layer and an optional dielectric capping layer may be formed over the three conductive portions. Portions of the second dielectric material layer and the first dielectric material layer are removed from within an area of a hole in a masking layer. The first dielectric material layer is laterally undercut to provide a micro-electro-mechanical-system (MEMS) switch comprising a conductive cantilever, a conductive plate, and a conductive actuator from the three conductive portions as portions of the first and second dielectric material layers are removed. The MEMS switch may be employed to provide mechanical switchable contact between the conductive cantilever and the conductive plate through an electrical signal on the conductive actuator.
摘要翻译： 第一介电材料层和第二电介质材料层形成在基板上。 在第二介电材料层内形成三个导电部分。 可以在三个导电部分上形成可选的第三介电材料层和可选的介电覆盖层。 第二介质材料层和第一介电材料层的一部分从掩模层中的孔的区域内被去除。 第一介电材料层被横向底切以提供微电子机械系统（MEMS）开关，其包括导电悬臂，导电板和导电致动器，作为第一和第二介电材料层的部分从三个导电部分 被删除。 MEMS开关可用于通过导电致动器上的电信号在导电悬臂与导电板之间提供机械可切换接触。
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公开(公告)号：US20120161255A1
公开(公告)日：2012-06-28
申请号：US12979592
申请日：2010-12-28
CPC分类号： B81C1/00293 , B81C2203/0145
摘要： Embodiments of the invention provide methods of sealing a micro electromechanical systems (MEMS) cavity and devices resulting therefrom. A first aspect of the invention provides a method of sealing a micro electromechanical systems (MEMS) cavity in a substrate, the method comprising: forming in a substrate a cavity filled with a sacrificial material; forming a lid over the cavity; forming at least one vent hole over the lid extending to the cavity; removing the sacrificial material from the cavity; depositing a first material onto the lid such that a size of at least one vent hole at a surface of the substrate is reduced but not sealed; and depositing a second material onto the first material to seal the at least one vent hole, wherein a MEMS cavity within the substrate and beneath the at least one vent hole substantially retains a pressure at which the at least one vent hole is sealed by the second material.
摘要翻译： 本发明的实施例提供了密封微机电系统（MEMS）腔和由此产生的装置的方法。 本发明的第一方面提供了一种密封衬底中的微机电系统（MEMS）空腔的方法，所述方法包括：在衬底中形成填充有牺牲材料的腔体; 在空腔上形成盖子; 在所述盖上形成延伸到所述空腔的至少一个通气孔; 从腔中去除牺牲材料; 将第一材料沉积到所述盖上，使得所述基板的表面处的至少一个通气孔的尺寸减小但不被密封; 以及将第二材料沉积到所述第一材料上以密封所述至少一个通气孔，其中所述基底内的MEMS空腔和所述至少一个通气孔下方基本上保持所述至少一个通气孔被所述第二通气孔密封的压力 材料。
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47.发明申请公开(公告)号：US20120151748A1
公开(公告)日：2012-06-21
申请号：US13404485
申请日：2012-02-24
CPC分类号： H01F17/0006 , H01F17/04 , H01F27/2847 , H01F41/04 , H01F41/041 , H01F41/045 , H01F2017/0053 , H01F2017/0073 , H01F2017/046 , H01L23/5227 , H01L23/528 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , Y10T29/49004 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073 , Y10T29/49156 , H01L2924/00
摘要： Embodiments disclosed include methods of designing an inductor. The inductor can include a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line.
摘要翻译： 公开的实施例包括设计电感器的方法。 电感器可以包括包括至少一个匝的导电线和位于导电线的区域的内部内的开口。
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公开(公告)号：US20120133006A1
公开(公告)日：2012-05-31
申请号：US12955220
申请日：2010-11-29
IPC分类号： H01L29/84
CPC分类号： H01G5/18 , B81B3/0072 , B81B2203/0118 , B81C2201/0167 , H01G5/16
摘要： In one embodiment, a semiconductor structure includes a beam positioned within a sealed cavity, the beam including: an upper insulator layer including one or more layers; and a lower insulator layer including one or more layers, wherein a composite stress of the upper insulator layer is different than a composite stress of the lower insulator layer, such that the beam bends.
摘要翻译： 在一个实施例中，半导体结构包括位于密封空腔内的光束，所述光束包括：包括一层或多层的上绝缘体层; 以及包括一层或多层的下绝缘体层，其中上绝缘体层的复合应力不同于下绝缘体层的复合应力，使得光束弯曲。
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公开(公告)号：US20120115303A1
公开(公告)日：2012-05-10
申请号：US13354371
申请日：2012-01-20
IPC分类号： H01L21/4763 , H01L21/02
CPC分类号： H01L21/76802 , H01L21/76807 , H01L23/5223 , H01L28/40 , H01L2221/1021 , H01L2221/1063
摘要： Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.
摘要翻译： 在集成电路中形成导线的方法。 所述方法包括在基板上的第一电介质层中形成导线; 在所述导线和所述第一介电层上形成介电阻挡层; 在阻挡层上形成第二电介质层; 在所述第二介电层上形成一个或多个图案化的光致抗蚀剂层; 执行反应离子蚀刻以蚀刻通过第二介电层而不穿过阻挡层的沟槽; 执行第二反应离子蚀刻以将沟槽延伸穿过阻挡层; 并且在执行第二反应离子蚀刻之后，去除一个或多个图案化的光致抗蚀剂层，使用还原等离子体或非氧化等离子体去除最后形成的图案化光致抗蚀剂层。 所述方法包括通过与金属 - 绝缘体 - 金属电容器类似的方法形成导线。
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公开(公告)号：US20120070979A1
公开(公告)日：2012-03-22
申请号：US12887737
申请日：2010-09-22
IPC分类号： H01L21/768 , C25D5/12 , C25D5/14 , H01L21/02
CPC分类号： H01L21/7684 , C25D3/38 , C25D5/10 , C25D5/12 , H01L21/2885 , H01L21/76877
摘要： The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.
摘要翻译： 本公开一般涉及半导体器件制造，更具体地涉及用于半导体器件制造中的电镀方法。 电镀方法包括：将处理后的基板浸入电解镀液中以在工艺衬底上形成第一金属层; 然后对所述工艺衬底上的衬垫进行第一化学机械抛光，然后将所述工艺衬底浸入所述电解电镀溶液中，以在所述第一金属层和所述衬垫上形成第二金属层; 以及对所述衬垫执行第二化学机械抛光。
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