公开(公告)号：US20050029600A1

公开(公告)日：2005-02-10

申请号：US10942014

申请日：2004-09-16

申请人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

发明人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/44 ,  H01L21/8238 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film

摘要翻译： 一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅 硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是 去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时 将氮气引入未被除去的二氧化硅的表面，依次溶解 并且去除引入氮的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面

公开(公告)号：US06723625B2

公开(公告)日：2004-04-20

申请号：US10251753

申请日：2002-09-23

申请人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

发明人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially. In forming the semiconductor device, a thin amorphous or polycrystalline silicon film can be provided on the gate insulating film, and a thin insulating film provided on the amorphous silicon film, with a thicker polycrystalline silicon film provided on or overlying the thin insulating film. Where the thin silicon film is amorphous silicon, it can then be polycrystallized, although it need not be. Also disclosed is a technique for selective crystallization of amorphous silicon layers, based upon layer thickness.

摘要翻译： 公开了一种半导体器件（例如非易失性半导体存储器件）及其形成方法。 该器件包括在栅极绝缘膜上具有非晶硅膜的第一层或多晶硅薄膜或非晶硅和多晶硅的组合的膜的栅电极（例如，浮栅电极）。 当膜包括多晶硅时，膜的厚度小于10nm。 可以在第一层上或覆盖第一层上提供较厚的多晶硅膜。 存储器件可以显着增加写入/擦除电流，而不会在施加应力之后增加低电场漏电流，这反过来大大降低了写入/擦除时间。 在形成半导体器件时，可以在栅极绝缘膜上提供薄的非晶或多晶硅膜，以及设置在非晶硅膜上的薄绝缘膜，其上设置有较厚的多晶硅膜或覆盖薄绝缘膜。 在薄硅膜是非晶硅的情况下，其然后可以多晶化，尽管不需要。 还公开了基于层厚度的非晶硅层的选择性结晶的技术。

公开(公告)号：US06710383B2

公开(公告)日：2004-03-23

申请号：US10005355

申请日：2001-12-07

申请人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

发明人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

IPC分类号： H01L2976

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.

摘要翻译： 提供如下配置的半导体器件。 在半导体衬底上形成作为绝缘膜的介电常数高于二氧化硅膜的氧化钛膜作为栅极绝缘膜，并且在其上设置栅电极，得到场效应晶体管。 氧化钛膜的栅极长度方向的端部位于栅电极的源极侧和漏极侧的各端部的内侧，氧化钛膜的端部位于 其中栅电极以平面构型与源区和漏区重叠。 该半导体器件以高速度工作，并且具有优异的短沟道特性和驱动电流。 此外，在半导体器件中，导入硅衬底的金属元素的量小。

公开(公告)号：US06656804B2

公开(公告)日：2003-12-02

申请号：US09894132

申请日：2001-06-29

申请人： Shimpei Tsujikawa ,  Jiro Yugami ,  Toshiyuki Mine ,  Masahiro Ushiyama

发明人： Shimpei Tsujikawa ,  Jiro Yugami ,  Toshiyuki Mine ,  Masahiro Ushiyama

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518

摘要： The present invention provides a MOS semiconductor device which enables gate leakage current reduction with a thinner gate dielectric film for higher speed, and a production method thereof. According to the present invention, a gate dielectric film 6 is made as follows: after forming a silicon nitride film 3 with a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxide 4 on the silicon nitride film 3, then this silicon oxide 4 is completely removed by exposure to a dissolving liquid. As a result, at depths between 0.12 nm and 0.5 nm from the top surface of the silicon nitride film 3 in the gate dielectric film 6 whose main constituent elements are silicon, nitrogen and oxygen, the nitrogen concentration is higher than the oxygen concentration. This enables the use of a thinner gate dielectric film with silicon, nitrogen and oxygen as main constituent elements while at the same time realizing reduction in leakage currents.

公开(公告)号：US06576943B1

公开(公告)日：2003-06-10

申请号：US09512827

申请日：2000-02-25

申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

IPC分类号： H01L27108

CPC分类号： G11C16/0433 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78642

摘要： A very thin semiconductor film is used for channels of semiconductor memory elements such that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. The amount of electrical charge accumulated in each charge accumulating region is used to change the conductance between a source region and a drain region of each read transistor structure. This conductance change is utilized for data storage. The thickness of the channel of the write transistor structure is preferably no more than 5 nm. According to one embodiment, the channel of the write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of the substrate.

摘要翻译： 非常薄的半导体膜用于半导体存储元件的通道，使得漏电流通过膜厚度方向的量子力学容纳效应而降低。 使用在每个电荷累积区域中累积的电荷量来改变每个读取的晶体管结构的源极区域和漏极区域之间的电导。 该电导变化用于数据存储。 写入晶体管结构的沟道的厚度优选不大于5nm。 根据一个实施例，写入晶体管的沟道由沉积在与衬底的主平面相交的表面上的半导体膜形成。

公开(公告)号：US06211531B1

公开(公告)日：2001-04-03

申请号：US09492171

申请日：2000-01-27

申请人： Kazuo Nakazato ,  Kiyoo Itoh ,  Hiroshi Mizuta ,  Toshikazu Shimada ,  Hideo Sunami ,  Tatsuya Teshima ,  Toshiyuki Mine ,  Ken Yamaguchi

发明人： Kazuo Nakazato ,  Kiyoo Itoh ,  Hiroshi Mizuta ,  Toshikazu Shimada ,  Hideo Sunami ,  Tatsuya Teshima ,  Toshiyuki Mine ,  Ken Yamaguchi

IPC分类号： H01L2906

CPC分类号： H01L27/10858 ,  B82Y10/00 ,  G11C11/16 ,  H01L21/28273 ,  H01L27/10808 ,  H01L27/1082 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/11 ,  H01L29/154 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78687 ,  H01L29/7881 ,  H01L29/882

摘要： A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

摘要翻译： 晶体管形式的可控导电器件包括源极和漏极区域5，其间延伸用于电荷载流子的导电路径P，用于控制沿导电路径的电荷载流子的栅极4和提供多个 导通路径中的隧道结结构，结果当晶体管处于其截止状态时，漏电流被多重隧道结构造阻塞。 描述了垂直和横向晶体管配置，以及使用晶体管的互补对和随机存取存储器单元。 描述了改进的栅极结构，其也适用于结合隧道势垒配置以在存储器节点上存储电荷的存储器件。

公开(公告)号：US4907046A

公开(公告)日：1990-03-06

申请号：US168490

申请日：1988-03-15

申请人： Yuzuru Ohji ,  Osamu Kasahara ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshiyuki Mine ,  Kunihiro Yagi

发明人： Yuzuru Ohji ,  Osamu Kasahara ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshiyuki Mine ,  Kunihiro Yagi

IPC分类号： H01L27/04 ,  F02B3/06 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/51 ,  H01L29/92 ,  H01L29/78 ,  H01L27/02 ,  H01L29/34

CPC分类号： H01L28/40 ,  H01L27/10808 ,  F02B3/06 ,  H01L29/51

摘要： A solid state device includes a transistor (A) and a capacitor (B). The capacitor is defined by a lower polycrystalline silicon layer or electrode (20), multiple dielectric layers (22), and an upper polycrystalline silicon layer or electrode (30). The dielectric layers are formed by vapor depositing a 3.6-18.6 nm thick layer of silicon nitride on the lower polycrystalline layer. Thicker silicon nitride layers increase the failure rate and decrease the capacitance (FIG. 8). More specifically, the silicon nitride layer is deposited on a thin, about 1 nm, oxidized film or surface (24) of the polycrystalline silicon layer. The silicon nitride layer is oxidized forming a silicon dioxide layer (28) until the silicon nitride layer is only about 3 nm thick. This forms on oxide layer that is 1-8.4 nm thick. If the silicon nitride layer is reduced below 3 nm, the polycrystalline silicon tends to oxidize rapidly reducing capacitance and increasing failure (FIG. 8).

摘要翻译： 固态器件包括晶体管（A）和电容器（B）。 电容器由下多晶硅层或电极（20），多个电介质层（22）和上多晶硅层或电极（30）限定。 电介质层通过在下多晶层上气相沉积3.6-18.6nm厚的氮化硅层形成。 较厚的氮化硅层增加故障率并降低电容（图8）。 更具体地，氮化硅层沉积在多晶硅层的薄的约1nm的氧化膜或表面（24）上。 氧化氮化硅层形成二氧化硅层（28），直到氮化硅层仅为约3nm厚。 这在氧化层上形成，厚度为1-8.4nm。 如果氮化硅层减小到3nm以下，则多晶硅容易迅速氧化，降低电容并增加故障（图8）。

公开(公告)号：US20150179744A1

公开(公告)日：2015-06-25

申请号：US14413435

申请日：2012-07-09

申请人： Toshiyuki Mine ,  Yasuhiro Shimamoto ,  Hirotaka Hamamura

发明人： Toshiyuki Mine ,  Yasuhiro Shimamoto ,  Hirotaka Hamamura

IPC分类号： H01L29/16 ,  H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/1608 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/12 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7926

摘要： The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.

摘要翻译： 本发明是在使用SiC衬底的SiC-MOSFET功率器件中使高通道迁移率和高阈值电压共存。 在栅极绝缘膜上具有电荷陷阱特性的分层绝缘膜的SiC MOSFET在SiC MOSFET的沟道长度方向上具有不规则的阈值电压，特别是具有最小阈值电压的较短区域 通道长度方向与具有其它阈值电压的区域相比较。

公开(公告)号：US20150044840A1

公开(公告)日：2015-02-12

申请号：US14381597

申请日：2012-03-30

申请人： Keisuke Kobayashi ,  Toshiyuki Mine ,  Hirotaka Hamamura

发明人： Keisuke Kobayashi ,  Toshiyuki Mine ,  Hirotaka Hamamura

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/16

CPC分类号： H01L29/66477 ,  H01L21/02057 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/046 ,  H01L21/049 ,  H01L21/26513 ,  H01L21/30604 ,  H01L29/1608 ,  H01L29/66053 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7827

摘要： In order to provide a method for producing a SiC-MOSFET capable of increasing Vth without deteriorating channel mobility, before forming a gate insulation film, (a) silicon carbide substrate is oxidized by a low temperature oxidation method represented by plasma oxidation to form a silicon oxide film. Next, (b) the silicon oxide film is removed. After repeating the processes (a) and (b) once or more, (c) the gate insulation film is formed.

摘要翻译： 为了提供能够增加Vth而不劣化沟道迁移率的SiC-MOSFET的制造方法，在形成栅极绝缘膜之前，（a）碳化硅衬底被等离子体氧化所代表的低温氧化法氧化，形成硅 氧化膜。 接下来，（b）去除氧化硅膜。 重复（a）和（b）工序一次以上后，（c）形成栅极绝缘膜。

公开(公告)号：US08790948B2

公开(公告)日：2014-07-29

申请号：US13303227

申请日：2011-11-23

申请人： Keiji Watanabe ,  Toshiyuki Mine ,  Akio Shima ,  Tomoko Sekiguchi ,  Ryuta Tsuchiya

发明人： Keiji Watanabe ,  Toshiyuki Mine ,  Akio Shima ,  Tomoko Sekiguchi ,  Ryuta Tsuchiya

IPC分类号： H01L21/00

CPC分类号： H01L31/02168 ,  B82Y20/00 ,  H01L31/0352 ,  H01L31/035236 ,  H01L31/055 ,  H01L31/075 ,  H01L31/1872 ,  Y02E10/52 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

摘要： In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.

摘要翻译： 在制造太阳能电池的现有方法中，难以制造具有具有结晶阱层并能够控制阱层的厚度的量子阱的太阳能电池。 形成具有非晶阱层的量子阱，其包含阻挡层和非晶阱层，然后对具有非晶阱层的量子阱退火，从而使非晶阱层结晶，形成具有结晶阱层的量子阱。 通过以1.26J / mm 2以上且28.8J / mm 2以下的能量密度施加到非晶质阱层的能量密度，可以形成结晶阱层，同时可以维持量子阱的层叠结构。