公开(公告)号：US07381642B2

公开(公告)日：2008-06-03

申请号：US11017168

申请日：2004-12-20

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L21/4763

CPC分类号： H01L24/11 ,  H01L21/768 ,  H01L21/76804 ,  H01L21/76838 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/60 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2224/05552 ,  H01L2924/00

摘要： The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

公开(公告)号：US07271489B2

公开(公告)日：2007-09-18

申请号：US10962963

申请日：2004-10-12

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/48

CPC分类号： H01L23/62 ,  H01L23/3192 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53252 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

公开(公告)号：US20070026631A1

公开(公告)日：2007-02-01

申请号：US11461416

申请日：2006-07-31

申请人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

发明人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

IPC分类号： H01L21/76

CPC分类号： H01L24/12 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05683 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/11912 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48673 ,  H01L2224/48683 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.

摘要翻译： 一种电路部件，包括半导体衬底，所述半导体衬底上的衬垫，在侧壁上的含钽层和所述焊盘的底表面，所述半导体衬底上的钝化层，所述钝化层中的露出所述衬垫的开口， 由所述开口暴露在所述垫上的含钛层，以及在所述含钛层上方的金层。

公开(公告)号：US20070023919A1

公开(公告)日：2007-02-01

申请号：US11383762

申请日：2006-05-17

申请人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

发明人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L23/525 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13183 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.

摘要翻译： 在具有至少在其顶表面上的接触层的集成电路（IC）衬底上制造焊盘结构。 钝化层覆盖IC基板的顶表面和接触层。 钝化层具有露出接触层的一部分的开口。 导电性粘合/阻挡层直接接合到接触层。 导电粘合/阻挡层延伸到钝化层的顶表面。 接合金属层层叠在导电性粘接/阻挡层上。

公开(公告)号：US20060267198A1

公开(公告)日：2006-11-30

申请号：US11420226

申请日：2006-05-25

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L23/5227 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/13022 ,  H01L2224/48463 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

摘要： A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are suited for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.

摘要翻译： 描述了一种新的互连方案，其包括IC芯片中的粗线和细线互连方案。 通常由选择性电镀技术形成的粗金属互连位于细线互连方案的顶部。 它对于长距离线路，时钟，电源和接地总线以及其他应用如高Q电感和旁路线尤其有用。 细线互连适用于局部互连。 粗线和细线互连的组合结构形成了一种新的互连方案，不仅提高了IC速度，而且降低了功耗。

公开(公告)号：US20060076687A1

公开(公告)日：2006-04-13

申请号：US10962963

申请日：2004-10-12

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/62 ,  H01L23/3192 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53252 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

公开(公告)号：US20060049483A1

公开(公告)日：2006-03-09

申请号：US10970871

申请日：2004-10-22

申请人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Chiu-Ming Chou

发明人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Chiu-Ming Chou

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/01019 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/014

摘要： A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

公开(公告)号：US08552559B2

公开(公告)日：2013-10-08

申请号：US11087955

申请日：2005-03-23

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76829 ,  H01L21/76837 ,  H01L21/76838 ,  H01L21/76873 ,  H01L21/76885 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.

摘要翻译： 描述了一种新的互连方案，其包括IC芯片中的粗线和细线互连方案。 通常由选择性电镀技术形成的粗金属互连位于细线互连方案的顶部。 它对于长距离线路，时钟，电源和接地总线以及其他应用如高Q电感和旁路线尤其有用。 细线互连更适合用于局部互连。 粗线和细线互连的组合结构形成了一种新的互连方案，不仅提高了IC速度，而且降低了功耗。

公开(公告)号：US08319354B2

公开(公告)日：2012-11-27

申请号：US13181255

申请日：2011-07-12

申请人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chien-Kang Chou ,  Chiu-Ming Chou ,  Ching-San Lin

发明人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chien-Kang Chou ,  Chiu-Ming Chou ,  Ching-San Lin

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L24/73 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05155 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05553 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/48463 ,  H01L2224/48477 ,  H01L2224/4943 ,  H01L2224/85051 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/4554

摘要： The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

摘要翻译： 本发明提供一种包括在所述钝化层上的互连结构的半导体芯片。 互连结构包括连接到由钝化层中的开口暴露的第二接触焊盘的第一接触焊盘。 金属凸块位于第一接触焊盘上并在多个半导体器件上，其中金属凸块具有超过50重量％的金并且具有在8和50微米之间的高度。

公开(公告)号：US08159074B2

公开(公告)日：2012-04-17

申请号：US13098379

申请日：2011-04-29

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Hsin-Jung Lo

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Hsin-Jung Lo

IPC分类号： H01L29/40

CPC分类号： H01L23/53238 ,  H01L23/3192 ,  H01L23/53252 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/056 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/48463 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/01039 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor chip includes first, second and third metal interconnects and an insulating layer over a semiconductor substrate. First, second and third openings in the insulating layer are over first, second and third contact points of the first, second and third metal interconnects, respectively. A fourth metal interconnect over the insulating layer connects the first and second contact points. The fourth metal interconnect includes a first metal layer and a second metal layer. The first metal layer is under but not at a sidewall of the second metal layer. The semiconductor chip includes a metal bump connected to the third contact point through the third opening, and a dielectric layer over the fourth metal interconnect and the insulating layer. No opening is in the dielectric layer on the fourth metal interconnect, and the metal bump has a top higher than a top surface of the dielectric layer.

摘要翻译： 半导体芯片包括第一，第二和第三金属互连以及半导体衬底上的绝缘层。 首先，绝缘层中的第二和第三开口分别位于第一，第二和第三金属互连的第一，第二和第三接触点上。 绝缘层上的第四金属互连件连接第一和第二接触点。 第四金属互连包括第一金属层和第二金属层。 第一金属层位于第二金属层的下侧但不在第二金属层的侧壁。 半导体芯片包括通过第三开口连接到第三接触点的金属凸块，以及在第四金属互连和绝缘层上的电介质层。 在第四金属互连上的电介质层中没有开口，并且金属凸块的顶部高于电介质层的顶表面。