公开(公告)号：US20110169173A1

公开(公告)日：2011-07-14

申请号：US13005051

申请日：2011-01-12

申请人： Sung-Ho MUN ,  Sun-Won Kang

发明人： Sung-Ho MUN ,  Sun-Won Kang

IPC分类号： H01L23/48

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/85196 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A wiring substrate for a semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface. The substrate has at least one slot from the first surface to the second surface that exposes chip pads of a semiconductor chip mounted to the first surface. The substrate has first and second regions divided by the slot. A plurality of bonding pads is arranged along both side portions of the slot and the bonding pads are connected to bonding wires that are drawn from the chip pads through the slot. First and second conductive patterns are respectively formed in the first and second regions and respectively connected to the at least one bonding pad. A merging pattern extends from the first region to the second region to electrically connect the first conductive pattern and the second conductive pattern. A merging wire electrically connects the merging pattern and the at least one chip pad.

摘要翻译： 用于半导体芯片的布线基板包括具有与第一表面相对的第一表面和第二表面的基板。 衬底具有从第一表面到第二表面的至少一个槽，其暴露安装到第一表面的半导体芯片的芯片焊盘。 衬底具有由槽划分的第一和第二区域。 多个接合焊盘沿着槽的两侧布置，并且焊盘与从芯片焊盘通过槽拉出的接合线连接。 第一和第二导电图案分别形成在第一和第二区域中，并且分别连接到至少一个接合焊盘。 合并图案从第一区域延伸到第二区域以电连接第一导电图案和第二导电图案。 合并线将合并图案与至少一个芯片垫电连接。

公开(公告)号：US20110079897A1

公开(公告)日：2011-04-07

申请号：US12894540

申请日：2010-09-30

申请人： Jin-Woo PARK ,  Eun-Chul Ahn ,  Dong-Kil Shin ,  Sun-Won Kang ,  Jong-Ho Lee

发明人： Jin-Woo PARK ,  Eun-Chul Ahn ,  Dong-Kil Shin ,  Sun-Won Kang ,  Jong-Ho Lee

IPC分类号： H01L23/48

CPC分类号： H01L24/06 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05018 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

摘要： In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode.

摘要翻译： 在集成电路（IC）芯片和具有其的倒装芯片封装中，不设置布线，并且第一电极焊盘不与IC芯片的焊盘区域中的布线接触。 因此，与焊盘区域中的布线无关，第一凸块结构与第一电极接触。 第二电极焊盘与IC芯片的伪焊盘区域中的布线接触。 因此，伪焊盘区域中的第二凸块结构在与第二电极下方的布线间隔开的接触点处与第二电极的上表面接触。

公开(公告)号：US07884458B2

公开(公告)日：2011-02-08

申请号：US11935953

申请日：2007-11-06

申请人： Sun-Won Kang ,  Seung-Duk Baek

发明人： Sun-Won Kang ,  Seung-Duk Baek

IPC分类号： H01L23/02

CPC分类号： H01G4/06 ,  H01G4/1227 ,  H01G4/308 ,  H01L23/50 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： A decoupling capacitor, a wafer stack package including the decoupling capacitor, and a method of fabricating the wafer stack package are provided. The decoupling capacitor may include a first electrode formed on an upper surface of a first wafer, a second electrode formed on a lower surface of a second wafer, and an adhesive material having a high dielectric constant and combining the first wafer with the second wafer. In the decoupling capacitor the first and second electrodes operate as two electrodes of the decoupling capacitor, and the adhesive material operates as a dielectric of the decoupling capacitor.

摘要翻译： 提供去耦电容器，包括去耦电容器的晶片堆叠封装以及制造晶片堆叠封装的方法。 去耦电容器可以包括形成在第一晶片的上表面上的第一电极，形成在第二晶片的下表面上的第二电极和具有高介电常数并且将第一晶片与第二晶片组合的粘合材料。 在去耦电容器中，第一和第二电极作为去耦电容器的两个电极工作，并且粘合材料作为去耦电容器的电介质。

公开(公告)号：US20100038778A1

公开(公告)日：2010-02-18

申请号：US12402123

申请日：2009-03-11

申请人： Kwang-Yong Lee ,  Sun-Won Kang ,  Sang-Hee Kim

发明人： Kwang-Yong Lee ,  Sun-Won Kang ,  Sang-Hee Kim

IPC分类号： H01L23/50 ,  H01L21/441

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/05552 ,  H01L2924/00014

摘要： A void that is created in a conductive electrode in a through hole that extends through an integrated circuit substrate can be used as a joining interface. For example, an integrated circuit structure includes an integrated circuit substrate having a conductive pad on a first face thereof, and a through hole that extends through the integrated circuit substrate from a second face of the integrated circuit substrate that is opposite to the first face and through the pad. A conductive electrode is provided in the through hole that extends from the second face to the first face through and onto the pad. The conductive electrode includes a void therein adjacent the second face. The void includes a void opening adjacent the second face that defines inner walls of the conductive electrode. A conductive material is provided in the void that directly contacts the inner walls of the conductive electrode. Related fabrication methods are also disclosed.

摘要翻译： 在贯通集成电路基板的通孔中的导电电极中产生的空隙可以用作接合界面。 例如，集成电路结构包括在其第一面上具有导电焊盘的集成电路基板和从集成电路基板的与第一面相反的第二面延伸穿过集成电路基板的通孔，以及 通过垫。 导电电极设置在通孔中，该通孔从第二面向第一面延伸并穿过衬垫。 导电电极包括与第二面相邻的空隙。 空隙包括邻近导电电极的内壁的邻近第二面的空隙。 导电材料设置在直接接触导电电极的内壁的空隙中。 还公开了相关的制造方法。

公开(公告)号：US07588964B2

公开(公告)日：2009-09-15

申请号：US11790173

申请日：2007-04-24

申请人： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

发明人： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/90 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83856 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.

摘要翻译： 半导体器件的层叠结构可以包括多个层叠的半导体器件，每个具有上表面和下表面以及从上表面到下表面突出的一个或多个通孔电极。 通孔电极可以具有从上表面突出的上部（头）和从下表面突出的下部（端部）。 层叠的半导体器件可以通过通孔电极彼此电连接。 可以在层叠的半导体器件之间形成第一粘合膜（例如，可图案化材料）和第二粘合膜（例如可刺穿材料）。 半导体器件的堆叠结构可以安装在具有安装专用粘合剂膜的印刷电路板（PCB）的上表面上以形成半导体器件封装。 安装的堆叠结构和PCB的上表面可以进一步被模制材料覆盖。

公开(公告)号：US20090146274A1

公开(公告)日：2009-06-11

申请号：US12259824

申请日：2008-10-28

申请人： Se-Young Yang ,  Sun-Won Kang ,  Yeo-Hoon Yoon

发明人： Se-Young Yang ,  Sun-Won Kang ,  Yeo-Hoon Yoon

IPC分类号： H01L23/495

CPC分类号： H01L23/49555 ,  H01L23/49575 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/182 ,  H05K1/183 ,  H05K3/3426 ,  H05K2201/09845 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10689 ,  H05K2201/10757 ,  Y02P70/613 ,  H01L2924/00

摘要： Integrated circuit packages include an integrated circuit mounting substrate having a hole that defines an inner wall of the integrated circuit mounting substrate. An integrated circuit is provided in the hole. A sinuous lead frame extends from the integrated circuit and is connected to the inner wall. The sinuous lead frame extends back and forth along a given direction, and may include a U- and/or V-shape, and round and/or jagged portions. Related packaging methods are also disclosed.

摘要翻译： 集成电路封装包括具有限定集成电路安装基板的内壁的孔的集成电路安装基板。 在孔中设置集成电路。 引线框架从集成电路延伸并连接到内壁。 弯曲的引线框架沿着给定的方向来回延伸，并且可以包括U形和/或V形，以及圆形和/或锯齿形部分。 还公开了相关的包装方法。

公开(公告)号：US20090001367A1

公开(公告)日：2009-01-01

申请号：US12116150

申请日：2008-05-06

申请人： Seung-Duk BAEK ,  Sun-Won KANG

发明人： Seung-Duk BAEK ,  Sun-Won KANG

IPC分类号： H01L23/482

CPC分类号： H01L23/5382 ,  H01L23/481 ,  H01L23/5258 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/4813 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor device in which a plurality of chips can be reliably stacked without reducing integration thereof. The semiconductor device includes a substrate on which a circuit is provided. Pads are disposed on the substrate for testing the circuit. At least one terminal is provided on the substrate. First conductors are used to electrically couple the pads and the circuit. Second conductors are used to electrically couple the at least one terminal and the circuit. A switching element is disposed in the middle of the first conductors to control the electrical connection between the pads and the circuit. A plurality of semiconductor devices may be stacked on top of one another to form a stacked module, wherein chip selection lines are formed, which extend to the bottom of each of the semiconductor devices to electrically couple chip selection terminals from among the at least one terminal of the semiconductor devices.

摘要翻译： 可以可靠地层叠多个芯片而不降低其一体化的半导体装置。 半导体器件包括其上设置有电路的衬底。 垫片设置在基板上用于测试电路。 在基板上设置至少一个端子。 第一导体用于电连接焊盘和电路。 第二导体用于电耦合至少一个端子和电路。 开关元件设置在第一导体的中间，以控制焊盘和电路之间的电连接。 多个半导体器件可以堆叠在彼此的顶部以形成堆叠的模块，其中形成芯片选择线，其延伸到每个半导体器件的底部，以将芯片选择端子从至少一个端子 的半导体器件。

公开(公告)号：US20080169545A1

公开(公告)日：2008-07-17

申请号：US11790173

申请日：2007-04-24

申请人： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

发明人： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/90 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83856 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.

摘要翻译： 半导体器件的层叠结构可以包括多个层叠的半导体器件，每个具有上表面和下表面以及从上表面到下表面突出的一个或多个通孔电极。 通孔电极可以具有从上表面突出的上部（头）和从下表面突出的下部（端部）。 层叠的半导体器件可以通过通孔电极彼此电连接。 可以在层叠的半导体器件之间形成第一粘合膜（例如，可图案化材料）和第二粘合膜（例如可刺穿材料）。 半导体器件的堆叠结构可以安装在具有安装专用粘合剂膜的印刷电路板（PCB）的上表面上以形成半导体器件封装。 安装的堆叠结构和PCB的上表面可以进一步被模制材料覆盖。

公开(公告)号：US20050104209A1

公开(公告)日：2005-05-19

申请号：US10977533

申请日：2004-10-28

申请人： Sun-Won Kang

发明人： Sun-Won Kang

IPC分类号： H01L23/12 ,  H01L23/13 ,  H01L23/24 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/48 ,  H01L23/52

CPC分类号： H01L23/50 ,  H01L23/13 ,  H01L23/24 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30107 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip package has a substrate that includes circuit lines provided on first and/or second surfaces, a power plane provided on the second surface, bump lands provided on the second surface and coupled to the circuit lines, and ball lands provided on the first surface. The package further has a semiconductor chip attached to the second surface of the substrate and electrically coupled to the circuit lines, and a dielectric layer provided on the second surface of the substrate. The dielectric layer surrounds laterally the chip, covers the power plane, and exposes the bump lands. The package further has a ground plane provided on both the chip and the dielectric layer, vertical connection bumps provided within the dielectric layer and on the bump lands and electrically coupled to the ground plane, and solder balls provided on the ball lands.

摘要翻译： 半导体芯片封装具有包括设置在第一和/或第二表面上的电路线的基板，设置在第二表面上的电源平面，设置在第二表面上并连接到电路线的凸起焊盘，以及设置在第一表面上的第一 表面。 封装还具有附接到衬底的第二表面并电耦合到电路线的半导体芯片，以及设置在衬底的第二表面上的电介质层。 电介质层横向包围芯片，覆盖电源平面，露出凸起焊盘。 封装还具有设置在芯片和电介质层两者上的接地平面，设置在电介质层内并且在凸起焊盘上并电耦合到接地平面的垂直连接凸块以及设置在球台上的焊球。

公开(公告)号：US08446016B2

公开(公告)日：2013-05-21

申请号：US13224670

申请日：2011-09-02

申请人： Sun-Won Kang ,  Seung-Duk Baek ,  Jong-Joo Lee

发明人： Sun-Won Kang ,  Seung-Duk Baek ,  Jong-Joo Lee

IPC分类号： H01L23/538

CPC分类号： H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

摘要： A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

摘要翻译： 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。