公开(公告)号：US07867876B2

公开(公告)日：2011-01-11

申请号：US12342393

申请日：2008-12-23

Applicant: Steven R. Codding ,  Timothy C. Krywanczyk ,  Timothy E. Neary ,  Edmund J. Sprogis

Inventor： Steven R. Codding ,  Timothy C. Krywanczyk ,  Timothy E. Neary ,  Edmund J. Sprogis

IPC: H01L21/30

CPC classification number: H01L21/6835 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/27436 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/09701 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 μm. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed.

Abstract translation: 在半导体基板的正面上形成C4研磨胶带和激光烧蚀粘合剂层。 然后将载体基板连接到激光烧蚀粘合剂层。 通过抛光或研磨使半导体衬底的背面变薄，在此期间，载体衬底提供机械支撑以使半导体衬底的薄化能够达到约25μm的厚度。 胶片框架胶带附着到减薄的半导体衬底的背面，激光烧蚀粘合剂层通过激光烧蚀，从而使载体衬底与C4研磨胶带的背面分离。 薄膜框架胶带，变薄的半导体衬底和C4研磨胶带的组装被切割。 通过紫外线照射C4研磨胶带以变得粘合性变差，随后被除去。

公开(公告)号：US07859114B2

公开(公告)日：2010-12-28

申请号：US12181467

申请日：2008-07-29

Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/06 ,  H01L23/053 ,  H01L23/12

CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684

Abstract: An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.

Abstract translation: 具有TWV触点的IC芯片和设计结构接触TWV并延伸穿过TWV上的第二介电层。 IC芯片可以包括基板; 穿过至少一个第一电介质层并进入衬底的贯通晶片通孔（TWV）; TWV触点接触TWV并延伸穿过TWV上的第二电介质层; 以及在所述第二电介质层上的第一金属布线层，所述第一金属布线层与所述TWV触点接触。

公开(公告)号：US07824961B2

公开(公告)日：2010-11-02

申请号：US12353549

申请日：2009-01-14

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L21/70

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US07768005B2

公开(公告)日：2010-08-03

申请号：US12129040

申请日：2008-05-29

Applicant: Vincenzo Condorelli ,  Claudius Feger ,  Kevin C. Gotze ,  Nihad Hadzic ,  John U. Knickerbocker ,  Edmund J. Sprogis

Inventor： Vincenzo Condorelli ,  Claudius Feger ,  Kevin C. Gotze ,  Nihad Hadzic ,  John U. Knickerbocker ,  Edmund J. Sprogis

IPC: H01L23/58

CPC classification number: H01L23/576 ,  H01L23/5383 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19103 ,  H01L2924/19107 ,  Y10T29/53039 ,  Y10T29/53052 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.

Abstract translation: 提供了一种物理上安全的处理组件，其包括安装在基板上的模具，以便将模具的电触点夹在模具和基板之间。 衬底设置有电连接到管芯触点并延伸穿过衬底的衬底触点和导电路径。 电导体围绕导电路径。 监控电路检测一个或多个电导体的连续性的断裂，并且优选地使组件不可操作。 优选地，提供环氧树脂封装以防止探测工具能够到达管芯或衬底接触。

公开(公告)号：US07700410B2

公开(公告)日：2010-04-20

申请号：US11759651

申请日：2007-06-07

Applicant: Kerry Bernstein ,  Timothy J. Dalton ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Richard Q. Williams

Inventor： Kerry Bernstein ,  Timothy J. Dalton ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Richard Q. Williams

IPC: H01L21/44

CPC classification number: H01L23/585 ,  H01L23/13 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13025 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/484 ,  H01L2224/49 ,  H01L2224/73257 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2224/78 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.

Abstract translation: 一种用于三维半导体芯片堆叠的芯片间插槽互连，特别是具有在半导体芯片上形成边缘连接的能力，其中半导体芯片安装在能够配备嵌入式电路的一个或多个芯片载体中。 此外，提供了用于在半导体芯片上制造边缘连接的独特方法，用于形成半导体芯片载体，以及用于制造新颖的半导体和组合芯片载体结构。

公开(公告)号：US20100029075A1

公开(公告)日：2010-02-04

申请号：US12181359

申请日：2008-07-29

Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L21/4763

CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

Abstract translation: 提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。 在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

公开(公告)号：US20080290525A1

公开(公告)日：2008-11-27

申请号：US11751105

申请日：2007-05-21

Applicant: Brent A. Anderson ,  Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Brent A. Anderson ,  Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L23/482 ,  H01L21/4763

CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/19043

Abstract: A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buried oxide and a layer of nitride lo separating these silicon structures. Vias are formed in the silicon carrier structure and through the oxide layer to the nitride layer and the walls of the via are passivated. The vias are filled with a filler material of either polysilicon or a conductive material. The substrate structure is then etched back to the nitride layer and the nitride layer is etched back to the filler material. Where the filler material is polysilicon, the polysilicon is etched away forming an open via to the top surface of the carrier wafer structure. The via is then backfilled with conductive material.

Abstract translation: 提供绝缘体上硅（SOI）结构，用于在硅晶片载体结构中形成通孔，而无需背面光刻。 SOI结构包括与硅衬底结构结合的硅晶片载体结构，其具有掩埋氧化物层和分离这些硅结构的氮化物层。 在硅载体结构中形成通孔，并且通过氧化物层到达氮化物层，并且通孔的壁被钝化。 通孔填充有多晶硅或导电材料的填充材料。 然后将衬底结构回蚀刻到氮化物层，氮化物层被回蚀刻到填充材料上。 当填充材料是多晶硅时，多晶硅被蚀刻掉，形成开口通孔到载体晶片结构的顶表面。 然后通孔用导电材料回填。

公开(公告)号：US20080231311A1

公开(公告)日：2008-09-25

申请号：US12129040

申请日：2008-05-29

Applicant: VINCENZO CONDORELLI ,  Claudius Feger ,  Kevin C. Gotze ,  Nihad Hadzic ,  John U. Knickerbocker ,  Edmund J. Sprogis

Inventor： VINCENZO CONDORELLI ,  Claudius Feger ,  Kevin C. Gotze ,  Nihad Hadzic ,  John U. Knickerbocker ,  Edmund J. Sprogis

IPC: G01R31/26

CPC classification number: H01L23/576 ,  H01L23/5383 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19103 ,  H01L2924/19107 ,  Y10T29/53039 ,  Y10T29/53052 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.

Abstract translation: 提供了一种物理上安全的处理组件，其包括安装在基板上的模具，以便将模具的电触点夹在模具和基板之间。 衬底设置有电连接到管芯触点并延伸穿过衬底的衬底触点和导电路径。 电导体围绕导电路径。 监控电路检测一个或多个电导体的连续性的断裂，并且优选地使组件不可操作。 优选地，提供环氧树脂封装以防止探测工具能够到达管芯或衬底接触。

公开(公告)号：US20080206960A1

公开(公告)日：2008-08-28

申请号：US11679226

申请日：2007-02-27

Applicant: Bing Dang ,  Mario J. Interrante ,  John Knickerbocker ,  Edmund J. Sprogis

Inventor： Bing Dang ,  Mario J. Interrante ,  John Knickerbocker ,  Edmund J. Sprogis

IPC: H01L21/30

CPC classification number: G01R31/2898 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/98 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A method for removing a thinned silicon structure from a substrate, the method includes selecting the silicon structure with soldered connections for removal; applying a silicon structure removal device to the silicon structure and the substrate, wherein the silicon structure removal device comprises a pre-determined temperature setpoint for actuation within a range from about eighty percent of a melting point of the soldered connections to about the melting point; heating the silicon structure removal device and the soldered connections of the silicon structure to within the range to actuate the silicon structure removal device; and removing the thinned silicon structure. Also disclosed is a structure including a plurality of layers, at least one layer including a thinned silicon structure and solder coupling the layer to another layer of the plurality; wherein the solder for each layer has a predetermined melting point.

Abstract translation: 一种用于从衬底去除薄化硅结构的方法，所述方法包括用焊接连接选择硅结构以便去除; 将硅结构去除装置施加到所述硅结构和所述衬底，其中所述硅结构去除装置包括用于在所述焊接连接的熔点的约80％到约熔点范围内的致动的预定温度设定点; 将硅结构去除装置和硅结构的焊接连接加热到致动硅结构去除装置的范围内; 并去除薄的硅结构。 还公开了包括多个层的结构，至少一个层，包括薄化硅结构和将该层耦合到多个层中的另一层的焊料; 其中每层的焊料具有预定的熔点。

公开(公告)号：US20080182361A1

公开(公告)日：2008-07-31

申请号：US12056808

申请日：2008-03-27

Applicant: Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L21/02

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.