公开(公告)号：US20180024867A1

公开(公告)日：2018-01-25

申请号：US15639037

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Ginger H. Gilsdorf ,  Karthik Kumar ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Mark A. Schmisseur

IPC: G06F9/50 ,  G06F12/10 ,  H04L12/24 ,  G06F13/40 ,  G06F13/16

CPC classification number: H04Q11/0005 ,  B25J15/0014 ,  B65G1/0492 ,  G02B6/3882 ,  G02B6/3893 ,  G02B6/3897 ,  G02B6/4292 ,  G02B6/4452 ,  G05D23/1921 ,  G05D23/2039 ,  G06F1/183 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0688 ,  G06F3/0689 ,  G06F8/65 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/4401 ,  G06F9/5016 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5072 ,  G06F9/5077 ,  G06F9/544 ,  G06F11/141 ,  G06F11/3414 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/10 ,  G06F12/109 ,  G06F12/1408 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/1694 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/409 ,  G06F13/42 ,  G06F13/4282 ,  G06F15/8061 ,  G06F16/9014 ,  G06F2209/5019 ,  G06F2209/5022 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/202 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2212/7207 ,  G06Q10/06 ,  G06Q10/06314 ,  G06Q10/087 ,  G06Q10/20 ,  G06Q50/04 ,  G07C5/008 ,  G08C17/02 ,  G08C2200/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1072 ,  G11C11/56 ,  G11C14/0009 ,  H03M7/30 ,  H03M7/3084 ,  H03M7/3086 ,  H03M7/40 ,  H03M7/4031 ,  H03M7/4056 ,  H03M7/4081 ,  H03M7/6005 ,  H03M7/6023 ,  H04B10/25 ,  H04B10/2504 ,  H04L9/0643 ,  H04L9/14 ,  H04L9/3247 ,  H04L9/3263 ,  H04L12/2809 ,  H04L29/12009 ,  H04L41/024 ,  H04L41/046 ,  H04L41/0813 ,  H04L41/082 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/145 ,  H04L41/147 ,  H04L41/5019 ,  H04L43/065 ,  H04L43/08 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L43/16 ,  H04L45/02 ,  H04L45/52 ,  H04L47/24 ,  H04L47/38 ,  H04L47/765 ,  H04L47/782 ,  H04L47/805 ,  H04L47/82 ,  H04L47/823 ,  H04L49/00 ,  H04L49/15 ,  H04L49/25 ,  H04L49/357 ,  H04L49/45 ,  H04L49/555 ,  H04L67/02 ,  H04L67/10 ,  H04L67/1004 ,  H04L67/1008 ,  H04L67/1012 ,  H04L67/1014 ,  H04L67/1029 ,  H04L67/1034 ,  H04L67/1097 ,  H04L67/12 ,  H04L67/16 ,  H04L67/306 ,  H04L67/34 ,  H04L69/04 ,  H04L69/329 ,  H04Q1/04 ,  H04Q11/00 ,  H04Q11/0003 ,  H04Q11/0062 ,  H04Q11/0071 ,  H04Q2011/0037 ,  H04Q2011/0041 ,  H04Q2011/0052 ,  H04Q2011/0073 ,  H04Q2011/0079 ,  H04Q2011/0086 ,  H04Q2213/13523 ,  H04Q2213/13527 ,  H04W4/023 ,  H04W4/80 ,  H05K1/0203 ,  H05K1/181 ,  H05K5/0204 ,  H05K7/1418 ,  H05K7/1421 ,  H05K7/1422 ,  H05K7/1442 ,  H05K7/1447 ,  H05K7/1461 ,  H05K7/1485 ,  H05K7/1487 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/1498 ,  H05K7/2039 ,  H05K7/20709 ,  H05K7/20727 ,  H05K7/20736 ,  H05K7/20745 ,  H05K7/20836 ,  H05K13/0486 ,  H05K2201/066 ,  H05K2201/10121 ,  H05K2201/10159 ,  H05K2201/10189 ,  Y02D10/14 ,  Y02D10/151 ,  Y02P90/30 ,  Y04S10/54 ,  Y10S901/01

Abstract: Technologies for dynamically allocating tiers of disaggregated memory resources include a compute device. The compute device is to obtain target performance data, determine, as a function of target performance data, memory tier allocation data indicative of an allocation of disaggregated memory sleds to tiers of performance, in which one memory sled of one tier is to act as a cache for another memory sled of a subsequent tier, send the memory tier allocation data and the target performance data to the corresponding memory sleds through a network, receive performance notification data from one of the memory sleds in the tiers, and determine, in response to receipt of the performance notification data, an adjustment to the memory tier allocation data.

公开(公告)号：US09792224B2

公开(公告)日：2017-10-17

申请号：US14921809

申请日：2015-10-23

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Martin P. Dimitrov ,  Thomas Willhalm

IPC: G06F12/08 ,  G06F12/1027 ,  G06F12/0862

CPC classification number: G06F12/1027 ,  G06F9/00 ,  G06F12/0862 ,  G06F13/16 ,  G06F2212/1024 ,  G06F2212/221

Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.

公开(公告)号：US20170185402A1

公开(公告)日：2017-06-29

申请号：US14757757

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Thomas Willhalm

IPC: G06F9/30

Abstract: A processor includes a core to execute an instruction to return an address of a bit-field in a packed bit array. The core includes logic to identify an index of the bit-field, identify a length of the bit-field, multiply the index and length, and return an address and bit-offset based upon a product of the index and length.

公开(公告)号：US20240396852A1

公开(公告)日：2024-11-28

申请号：US18792276

申请日：2024-08-01

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Mark A. Schmisseur ,  Timothy Verrall

IPC: H04L47/765 ,  G06F9/50 ,  G06N20/00 ,  H04L47/70 ,  H04L47/83

Abstract: There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.

公开(公告)号：US12132825B2

公开(公告)日：2024-10-29

申请号：US17561558

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Timothy Verrall ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar ,  Ned M. Smith ,  Rajesh Poornachandran ,  Kapil Sood ,  Tarun Viswanathan ,  John J. Browne ,  Patrick Kutch

IPC: H04L9/08

CPC classification number: H04L9/083 ,  H04L9/0836 ,  H04L9/0891 ,  H04L9/0894 ,  H04L9/0897

Abstract: Technologies for accelerated key caching in an edge hierarchy include multiple edge appliance devices organized in tiers. An edge appliance device receives a request for a key, such as a private key. The edge appliance device determines whether the key is included in a local key cache and, if not, requests the key from an edge appliance device included in an inner tier of the edge hierarchy. The edge appliance device may request the key from an edge appliance device included in a peer tier of the edge hierarchy. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys in the key cache for eviction. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys for pre-fetching. Those functions of the edge appliance device may be performed by an accelerator such as an FPGA. Other embodiments are described and claimed.

公开(公告)号：US11880714B2

公开(公告)日：2024-01-23

申请号：US17521592

申请日：2021-11-08

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Ned Smith ,  Thomas Willhalm ,  Timothy Verrall

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F1/26 ,  G06F9/455 ,  G06F1/3293

CPC classification number: G06F9/5027 ,  G06F1/26 ,  G06F1/3293 ,  G06F9/45558 ,  G06F9/48 ,  G06F9/485 ,  G06F9/4806 ,  G06F9/4843 ,  G06F9/4856 ,  G06F9/4881 ,  G06F9/4893 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/505 ,  G06F9/5044 ,  G06F9/5055 ,  G06F9/5061 ,  G06F9/5072 ,  G06F9/5094 ,  G06F9/54 ,  G06F9/547 ,  G06F2009/45595

Abstract: Technologies for providing dynamic selection of edge and local accelerator resources includes a device having circuitry to identify a function of an application to be accelerated, determine one or more properties of an accelerator resource available at the edge of a network where the device is located, and determine one or more properties of an accelerator resource available in the device. Additionally, the circuitry is to determine a set of acceleration selection factors associated with the function, wherein the acceleration factors are indicative of one or more objectives to be satisfied in the acceleration of the function. Further, the circuitry is to select, as a function of the one or more properties of the accelerator resource available at the edge, the one or more properties of the accelerator resource available in the device, and the acceleration selection factors, one or more of the accelerator resources to accelerate the function.

公开(公告)号：US11789878B2

公开(公告)日：2023-10-17

申请号：US16721706

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Benjamin Graniello ,  Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm

IPC: G06F13/16 ,  G06F3/06 ,  G06F15/78 ,  G06F11/30 ,  G06F12/02 ,  G06F9/50

CPC classification number: G06F13/1663 ,  G06F3/061 ,  G06F3/067 ,  G06F3/0635 ,  G06F3/0685 ,  G06F9/5016 ,  G06F11/3037 ,  G06F12/0246 ,  G06F13/1678 ,  G06F15/7807

Abstract: Methods, apparatus and systems for adaptive fabric allocation for local and remote emerging memories-based prediction schemes. In conjunction with performing memory transfers between a compute host and memory device connected via one or more interconnect segments, memory read and write traffic is monitored for at least one interconnect segment having reconfigurable upstream lanes and downstream lanes. Predictions of expected read and write bandwidths for the at least one interconnect segment are then made. Based on the expected read and write bandwidths, the upstream lanes and downstream lanes are dynamically reconfigured. The interconnect segments include interconnect links such as Compute Exchange Link (CXL) flex buses and memory channels for local memory implementations, and fabric links for remote memory implementations. For local memory, management messages may be used to provide telemetry information containing the expected read and write bandwidths. For remote memory, telemetry information is provided to a fabric management component that is used to dynamically reconfigure one or more fabric links.

公开(公告)号：US11675326B2

公开(公告)日：2023-06-13

申请号：US17330738

申请日：2021-05-26

Applicant: Intel Corporation

Inventor： Nicolas A. Salhuana ,  Karthik Kumar ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Narayan Ranganathan

IPC: G06F9/06 ,  G05B19/042 ,  H03K19/17732 ,  G06F8/41 ,  H03K19/17728

CPC classification number: G05B19/0426 ,  G06F8/44 ,  G06F8/456 ,  H03K19/17728 ,  H03K19/17732 ,  G05B2219/21109

Abstract: In one embodiment, an apparatus comprises a fabric controller of a first computing node. The fabric controller is to receive, from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the second computing node via the network fabric.

公开(公告)号：US11609859B2

公开(公告)日：2023-03-21

申请号：US16950233

申请日：2020-11-17

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Brian J. Slechta

IPC: G06F12/0891 ,  G06F9/30

Abstract: Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.

公开(公告)号：US11456966B2

公开(公告)日：2022-09-27

申请号：US17500543

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Mark A. Schmisseur ,  Timothy Verrall

IPC: G06F15/173 ,  H04L47/765 ,  H04L47/70 ,  G06F9/50 ,  G06N20/00

Abstract: There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (Al) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the Al circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.