公开(公告)号：US20130277851A1

公开(公告)日：2013-10-24

申请号：US13917982

申请日：2013-06-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu ,  Pandi Chelvam Marimuthu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76802 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Abstract translation: 半导体器件具有布置在半导体管芯的周边区域中的模块化互连单元或互连结构。 密封剂沉积在半导体管芯和互连结构上。 在半导体管芯和互连结构之上形成第一绝缘层。 在互连结构上的第一绝缘层中形成多个开口。 开口的间距为40微米。 开口包括圆形，环形，十字形或格子形状。 导电层沉积在第一绝缘层上。 导电层包括平坦表面。 在导电层上形成第二绝缘层。 去除一部分密封剂以露出半导体管芯和互连结构。 模块化互连单元包括垂直互连结构。 模块化互连单元形成围绕半导体管芯的互锁图案的一部分。

公开(公告)号：US20130147019A1

公开(公告)日：2013-06-13

申请号：US13766493

申请日：2013-02-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng ,  Xusheng Bao

IPC: H01L23/29

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/28 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14135 ,  H01L2224/221 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

Abstract translation: 多个半导体管芯安装到临时载体上。 密封剂沉积在半导体管芯和载体上。 密封剂的一部分被指定为模具之间的锯道，并且密封剂的一部分被指定为围绕密封剂的周边的基底边缘。 载体被移除。 在模具，锯条和基板边缘上形成第一绝缘层。 在第一绝缘层上形成第一导电层。 在第一导电层和第一绝缘层上形成第二绝缘层。 通过第一绝缘层和锯条将密封剂分离，以分离半导体管芯。 可以在锯条的相对侧的第一绝缘层中形成通道或网状图案，或者第一绝缘层覆盖整个锯条和半导体管芯周围的成型区域。

公开(公告)号：US09847324B2

公开(公告)日：2017-12-19

申请号：US14730030

申请日：2015-06-03

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L25/00 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L25/10 ,  H01L25/07 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/04 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/03003 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/0613 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/82005 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/13015 ,  H01L2224/81

Abstract: A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure.

公开(公告)号：US09437552B2

公开(公告)日：2016-09-06

申请号：US14449869

申请日：2014-08-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng ,  Xusheng Bao

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/28 ,  H01L21/78 ,  H01L23/29 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/28 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14135 ,  H01L2224/221 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

公开(公告)号：US09401331B2

公开(公告)日：2016-07-26

申请号：US14267800

申请日：2014-05-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Xusheng Bao ,  Kang Chen ,  Jianmin Fang

IPC: H01L23/482 ,  H01L23/538 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/5386 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.

Abstract translation: 通过在载体上形成第一导电层制成半导体器件。 第一导电层具有与第一导电层的第二区域电隔离的第一区域。 在第一导电层的第一区域上形成导电柱。 半导体管芯或部件安装到第一导电层的第二区域。 第一密封剂沉积在半导体管芯上并且围绕导电柱。 在第一密封剂上形成第一互连结构。 第一互连结构电连接到导电柱。 载体被移除。 去除第一导电层的一部分。 第一导电层的剩余部分包括互连线和UBM垫。 在第一导电层的剩余部分上形成第二互连结构被去除。

公开(公告)号：US09368563B2

公开(公告)日：2016-06-14

申请号：US14092304

申请日：2013-11-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kai Liu ,  Kang Chen

IPC: H01L27/00 ,  H01L49/02 ,  H01L21/56 ,  H01L23/522 ,  H01L23/538 ,  H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H03H1/00 ,  H01L23/498

CPC classification number: H01L28/10 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1206 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/30107 ,  H03H2001/0078 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Abstract translation: 半导体器件具有第一半导体管芯。 在第一半导体管芯上形成第一电感器。 第二电感器形成在第一电感器上并与第一电感器对准。 在第一半导体管芯和第一和第二电感器上形成绝缘层。 导电桥形成在绝缘层之上并电连接在第二电感器和第一半导体管芯之间。 在一个实施例中，半导体器件具有第二半导体管芯，并且在第一和第二半导体管芯之间形成导电层。 在另一实施例中，在第一半导体管芯上形成电容器。 在另一个实施例中，绝缘层在第一半导体管芯的覆盖区之上具有第一厚度，并且第二厚度小于第一半导体管芯的覆盖区之外的第一厚度。

公开(公告)号：US20150287708A1

公开(公告)日：2015-10-08

申请号：US14745203

申请日：2015-06-19

Applicant: STATS ChipPAC, LTD.

Inventor： Yaojian Lin ,  Kang Chen ,  Seung Wook Yoon

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/03 ,  H01L2224/03002 ,  H01L2224/03003 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0613 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2224/82005 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

Abstract translation: 半导体器件具有沉积在半导体管芯的第一表面上并且围绕半导体管芯的密封剂。 在半导体管芯的与第一表面相对的第二表面上形成第一绝缘层。 导电层形成在第一绝缘层上。 通过半导体管芯的覆盖区外的密封剂形成互连结构，并电连接到导电层。 第一绝缘层包括光学透明或半透明材料。 半导体管芯包括被配置为接收穿过第一绝缘层的外部刺激的传感器。 在半导体管芯的第一表面上形成第二绝缘层。 通过半导体管芯的覆盖区外的第一绝缘层形成导电通孔。 多个层叠的半导体器件通过互连结构电连接。

公开(公告)号：US09087930B2

公开(公告)日：2015-07-21

申请号：US14274599

申请日：2014-05-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。

公开(公告)号：US08994185B2

公开(公告)日：2015-03-31

申请号：US14043751

申请日：2013-10-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H05K1/18 ,  H01L23/31

CPC classification number: H01L24/06 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. A conductive micro via array is formed outside a footprint of the semiconductor die and over the semiconductor die and encapsulant. A first through-mold-hole (TMH) is formed including a step-through-hole structure through the encapsulant to expose the conductive micro via array. An insulating layer is formed over the semiconductor die and the encapsulant. A micro via array is formed through the insulating layer and outside the footprint of the semiconductor die. A conductive layer is formed over the insulating layer. A conductive ring is formed comprising the conductive micro via array. A second TMH is formed partially through the encapsulant to a recessed surface of the encapsulant. A third TMH is formed through the encapsulant and extending from the recessed surface of the encapsulant to the conductive micro via array.

Abstract translation: 半导体器件包括半导体管芯。 密封剂沉积在半导体管芯上。 导电微通孔阵列形成在半导体管芯的覆盖区之外并且在半导体管芯和密封剂之上。 形成第一通孔模具（TMH），其包括通过密封剂的通孔结构，以暴露导电微通孔阵列。 在半导体管芯和密封剂上形成绝缘层。 微通孔阵列通过绝缘层形成，并且在半导体管芯的覆盖区外部形成。 在绝缘层上形成导电层。 形成包括导电微通孔阵列的导电环。 第二TMH部分地通过密封剂形成到密封剂的凹陷表面。 通过密封剂形成第三TMH，并从密封剂的凹陷表面延伸到导电微通孔阵列。

公开(公告)号：US20150084213A1

公开(公告)日：2015-03-26

申请号：US14036193

申请日：2013-09-25

Applicant: STATS ChipPAC, Ltd.

Inventor： Kian Meng Heng ,  Hin Hwa Goh ,  Jose Alvin Caparas ,  Kang Chen ,  Seng Guan Chow ,  Yaojian Lin

IPC: H01L21/56 ,  H01L23/28

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/19 ,  H01L24/48 ,  H01L24/49 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.

Abstract translation: 半导体器件具有设置在衬底上方的加强层的衬底。 基板具有圆形或矩形形状。 多个半导体管芯设置在衬底的一部分上，同时留下没有半导体管芯的衬底的开放区域。 没有半导体管芯的基板的开放区域包括半导体管芯之间的中心区域或间隙位置。 半导体管芯围绕衬底的周边设置。 密封剂沉积在半导体管芯和衬底上。 去除衬底并在半导体管芯上方形成互连结构。 通过使没有半导体管芯的基板的预定区域离开，在去除衬底之后，半导体管芯的CTE与封装物的复合晶片的CTE之间的任何失配的翘曲效应降低。