公开(公告)号：US20170186730A1

公开(公告)日：2017-06-29

申请号：US15152469

申请日：2016-05-11

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Guilian Gao

IPC: H01L25/065 ,  H01L21/78 ,  H01L21/683 ,  H01L23/00 ,  H01L21/768 ,  H01L21/306 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L24/94 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/1436

Abstract: Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.

公开(公告)号：US20170179046A1

公开(公告)日：2017-06-22

申请号：US15449993

申请日：2017-03-05

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Ilyas Mohammed ,  Masud Beroz

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/02

CPC classification number: H01L23/562 ,  H01L21/02002 ,  H01L21/02035 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02414 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/19 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L27/0207 ,  H01L33/005 ,  H01L33/0062 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00

Abstract: In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

公开(公告)号：US20170117243A1

公开(公告)日：2017-04-27

申请号：US15332533

申请日：2016-10-24

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Gabriel Z. Guevara ,  Xuan Li ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/16 ,  H01L21/565 ,  H01L23/315 ,  H01L24/27 ,  H01L24/32 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/85355 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755

Abstract: A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.

公开(公告)号：US20170099733A1

公开(公告)日：2017-04-06

申请号：US15380172

申请日：2016-12-15

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H05K1/09 ,  H01L21/48 ,  H05K1/11 ,  H01L23/498

CPC classification number: H05K1/097 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/113 ,  H05K1/165 ,  H05K3/188 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/5313 ,  H01L2924/00

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

公开(公告)号：US20170018485A1

公开(公告)日：2017-01-19

申请号：US15209034

申请日：2016-07-13

Applicant: Invensas Corporation

Inventor： Ashok S. Prabhu ,  Rajesh Katkar ,  Liang Wang ,  Cyprian Emeka Uzoh

IPC: H01L23/495 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49541 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/18

Abstract: A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of a plurality of planes. A leadframe interconnect joined to a contact at a front surface of each chip may extend to a position beyond the edge surface of the respective microelectronic element. The chip stack is mounted to support element at an angle such that edge surfaces of the chips face a major surface of the support element that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. The leadframe interconnects are electrically coupled at ends thereof to corresponding contacts at a surface of the support element.

Abstract translation: 微电子组件包括一组微电子元件，例如半导体芯片，每个半导体芯片具有限定多个平面的相应平面的前表面。 连接到每个芯片的前表面处的触点的引线框互连可以延伸到超过相应微电子元件的边缘表面的位置。 芯片堆叠以一定角度安装到支撑元件，使得芯片的边缘表​​面面向支撑元件的主表面，该主表面限定横向于，即不平行于多个平行平面的第二平面。 引线框互连在其端部电耦合到支撑元件的表面处的相应触点。

公开(公告)号：US20160365302A1

公开(公告)日：2016-12-15

申请号：US15248726

申请日：2016-08-26

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Hong Shen ,  Cyprian Emeka Uzoh ,  Belgacem Haba

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/04

CPC classification number: H01L23/498 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/1427 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2224/81

Abstract: A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The forming of the circuit structure can include forming a first dielectric layer coupled to the carrier. The first dielectric layer can include front contacts configured for joining with contacts of one or more microelectronic elements, and first traces. The forming of the circuit structure can include forming rear conductive elements at the rear surface coupled with the front contacts through the first traces. The forming of the substrate can include forming a dielectric element directly on the rear surface. The dielectric element can have first conductive elements facing the rear conductive elements and joined thereto. The dielectric element can include second traces coupled with the first conductive elements. The forming of the substrate can include forming terminals at a surface of the substrate.

Abstract translation: 制造组件的方法可以包括形成限定前表面和后表面的电路结构，以及在后表面上形成衬底。 电路结构的形成可以包括形成耦合到载体的第一介电层。 第一电介质层可以包括构造成与一个或多个微电子元件的触点和第一迹线接合的前触点。 电路结构的形成可以包括通过第一迹线在与前触点耦合的后表面处形成后导电元件。 基板的形成可以包括直接在后表面上形成电介质元件。 电介质元件可以具有面向后导电元件并与其连接的第一导电元件。 电介质元件可以包括与第一导电元件耦合的第二迹线。 基板的形成可以包括在基板的表面上形成端子。

公开(公告)号：US09478504B1

公开(公告)日：2016-10-25

申请号：US14745237

申请日：2015-06-19

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Rajesh Katkar ,  Charles G. Woychik ,  Guilian Gao

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/053 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L23/053 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16153 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16315 ,  H01L2924/1632 ,  H01L2924/167 ,  H01L2924/16787 ,  H01L2924/16788 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/01029 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the assembly, possibly to the encapsulant (474) at the top. The lid's legs (520) surround the cavity and extend down below the top surface of the interposer's substrate (420S), possibly to the level of the bottom surface of the substrate or lower. The legs (520) may or may not be attached to the interposer/die assembly. In fabrication, the interposer wafer (420SW) has trenches (478) which receive the lid's legs during the lid placement. The interposer wafer is later thinned to remove the interposer wafer portion below the legs and to dice the interposer wafer. The thinning process also exposes, on the bottom, conductive vias (450) passing through the interposer substrate. Other features are also provided.

Abstract translation: 模具（110）附接到插入件（420），并且插入器/模具组件被放置在盖腔（510）中。 盖（210）附接到组件的顶部，可能附接到顶部的密封剂（474）。 盖的腿（520）围绕空腔并且向下延伸到插入器的衬底（420S）的顶表面下方，可能地到衬底的底表面的高度或更低。 腿（520）可以或可以不附接到插入件/模具组件。 在制造中，插入器晶片（420SW）具有在盖放置期间接收盖的腿的沟槽（478）。 中间层晶片稍后变薄以去除腿下方的插入片晶片部分并且切割插入片晶片。 薄化工艺还在底部暴露穿过内插衬底的导电通孔（450）。 还提供其他功能。

公开(公告)号：US20160260696A1

公开(公告)日：2016-09-08

申请号：US15153188

申请日：2016-05-12

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Liang Wang

IPC: H01L25/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15333 ,  H01L2924/014 ,  H01L2924/00

Abstract: A microelectronic assembly can be made by joining first and second subassemblies by electrically conductive masses to connect electrically conductive elements on support elements of each subassembly. A patterned layer of photo-imageable material may overlie a surface of one of the support elements and have openings with cross-sectional dimensions which are constant or monotonically increasing with height from the surface of that support element, where the masses extend through the openings and have dimensions defined thereby. An encapsulation can be formed by flowing an encapsulant into a space between the joined first and second subassemblies.

公开(公告)号：US09412806B2

公开(公告)日：2016-08-09

申请号：US14304535

申请日：2014-06-13

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Hong Shen ,  Cyprian Emeka Uzoh

IPC: H01L27/01 ,  H01L49/02

CPC classification number: H01L28/65 ,  H01L28/90 ,  H01L28/92 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15153 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00012

Abstract: In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.

Abstract translation: 在一个实施例中，制造3D金属 - 绝缘体 - 金属（MIM）电容器的方法包括提供具有表面的基板，在表面上形成直立杆或脊的阵列，在表面上沉积第一层电导体， 所述棒或脊的阵列，用电介质层涂覆所述第一导电层，以及在所述电介质层上沉积第二层电导体。 在一些实施例中，杆或脊的阵列可以由光致抗蚀剂材料制成，并且在另一些实施例中，可以包括接合线。

公开(公告)号：US20160218057A1

公开(公告)日：2016-07-28

申请号：US14602984

申请日：2015-01-22

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H01L23/498 ,  H05K3/18 ,  H05K1/16 ,  H01L21/48 ,  H05K1/11

CPC classification number: H05K1/097 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/113 ,  H05K1/165 ,  H05K3/188 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/5313 ,  H01L2924/00

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

Abstract translation: 内插器电路（130）由可能牺牲的基板（210）形成，所述牺牲基板（210）从由导电涂层（130“）覆盖的多孔芯（130'）形成，所述导电涂层增加导电性。 核心由纳米颗粒油墨印刷。 然后形成支撑件（120S），例如 通过模制，以机械地稳定电路。 在形成电路或支撑件的同时，可以使用磁场来稳定电路。 还提供其他功能。