公开(公告)号：US08569865B2

公开(公告)日：2013-10-29

申请号：US13424792

申请日：2012-03-20

申请人： Matthias Stecher

发明人： Matthias Stecher

IPC分类号： H01L21/70

CPC分类号： H01L21/761 ,  H01L21/823878 ,  H01L27/0629 ,  H01L29/7809 ,  H01L29/7811

摘要： An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.

摘要翻译： 公开了集成电路和制造方法。 一个实施例在半导体阱中形成反向电流复合物，使得形成有害的反向电流的电荷载流子不能流入衬底。

公开(公告)号：US20130267080A1

公开(公告)日：2013-10-10

申请号：US13798674

申请日：2013-03-13

申请人： MAXPOWER SEMICONDUCTOR, INC.

发明人： Mohamed N. Darwish

IPC分类号： H01L21/20 ,  H01L21/28

CPC分类号： H01L29/7802 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/2003 ,  H01L21/265 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823885 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66537 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835

摘要： A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type. The method further includes implanting ions into the thermal oxide layer, forming a second insulator layer, removing the second insulator layer from a portion of the trench, and forming an oxide layer in the trench and on the epitaxial layer. Moreover, the method includes forming a material in the trench, forming a second gate oxide layer over the material, and patterning the second gate oxide layer.

公开(公告)号：US20130228854A1

公开(公告)日：2013-09-05

申请号：US13778301

申请日：2013-02-27

申请人： MICROCHIP TECHNOLOGY INCORPORATED

发明人： Greg A. Dix ,  Dan Grimm

IPC分类号： H01L29/78

CPC分类号： H01L29/7809 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate.

摘要翻译： 场效应晶体管（FET）单元结构具有衬底，衬底上具有第一导电类型的外延层，第二导电类型的第一和第二基极区布置在外延层内或阱内并且间隔开，以及第一和第 第一导电类型的第二源极区域分别布置在第一和第二基极区域内。 此外，通过绝缘层与外延层绝缘的栅极结构被设置并布置在第一和第二基极区域之间的区域上方并且至少部分地覆盖第一和第二基极区域，并且漏极接触从顶部 器件通过外延层将顶部接触或金属层与衬底耦合。

公开(公告)号：US20130203225A1

公开(公告)日：2013-08-08

申请号：US13725789

申请日：2012-12-21

申请人： Alpha & Omega Semiconductor Limited

发明人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

IPC分类号： H01L29/872 ,  H01L29/78

CPC分类号： H01L29/7811 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/8725

摘要： Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into the drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench.

摘要翻译： 制造半导体器件包括：在覆盖半导体衬底的外延层中形成栅极沟槽; 在栅极沟槽中沉积栅极材料; 形成身体 形成一个来源; 形成有源区接触沟槽，其通过所述源极和所述主体延伸到所述漏极中; 在有源区接触沟槽的底部区域的外延层中形成肖特基势垒控制层; 以及将接触电极设置在有源区接触沟槽内。

公开(公告)号：US08502314B2

公开(公告)日：2013-08-06

申请号：US13091681

申请日：2011-04-21

申请人： Thomas E. Grebs ,  Jayson S. Preece

发明人： Thomas E. Grebs ,  Jayson S. Preece

IPC分类号： H01L29/76

CPC分类号： H01L23/4824 ,  H01L24/05 ,  H01L24/13 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/131 ,  H01L2924/01327 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014

摘要： This document discusses, among other things, a semiconductor device including first and second conductive layers, the first conductive layer including a gate runner and a drain contact and the second conductive layer including a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner. A first surface of the semiconductor device can include a gate pad coupled to the gate runner and a drain pad coupled to the drain contact and the drain conductor.

摘要翻译： 该文件尤其涉及包括第一和第二导电层的半导体器件，第一导电层包括栅极流道和漏极接触，第二导电层包括漏极导体，漏极导体的至少一部分覆盖在 至少一部分闸门跑步者。 半导体器件的第一表面可以包括耦合到栅极流道的栅极焊盘和耦合到漏极接触和漏极导体的漏极焊盘。

公开(公告)号：US08487371B2

公开(公告)日：2013-07-16

申请号：US13074921

申请日：2011-03-29

申请人： Daniel M. Kinzer ,  Steven Sapp ,  Chung-Lin Wu ,  Oseob Jeon ,  Bigildis Dosdos

发明人： Daniel M. Kinzer ,  Steven Sapp ,  Chung-Lin Wu ,  Oseob Jeon ,  Bigildis Dosdos

IPC分类号： H01L29/66 ,  H01L23/62 ,  H01L27/088 ,  H01L21/338

CPC分类号： H01L29/7827 ,  H01L24/13 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/131 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance RDS(on) include using a two-metal drain contact technique. The RDS(on) is further improved by using a through-silicon-via (TSV) technique to form a drain contact or by using a copper layer closely connected to the drain drift.

摘要翻译： 具有晶体管的晶体管的晶体管的晶体管的一侧制造晶圆级芯片级封装（WLCSP）器件的系统和方法仍然具有优异的电气性能，低漏极 - 源极电阻RDS（on）包括使用 双金属漏极接触技术。 通过使用穿硅通孔（TSV）技术来形成漏极接触或通过使用紧密连接到漏极漂移的铜层来进一步改善RDS（on）。

公开(公告)号：US08410599B2

公开(公告)日：2013-04-02

申请号：US12756915

申请日：2010-04-08

申请人： Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

发明人： Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

IPC分类号： H01L23/04

CPC分类号： H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

摘要翻译： 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

公开(公告)号：US20130056821A1

公开(公告)日：2013-03-07

申请号：US13223603

申请日：2011-09-01

申请人： YUAN-SHUN CHANG ,  YI-YUN TSAI ,  KAO-WAY TU

发明人： YUAN-SHUN CHANG ,  YI-YUN TSAI ,  KAO-WAY TU

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7809 ,  H01L21/74 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7812 ,  H01L29/7813

摘要： A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.

摘要翻译： 提供了一种在轻掺杂衬底上的沟槽功率半导体器件。 该器件具有基极，至少包括栅极沟槽，多个第一重掺杂区域，体区域，源极掺杂区域，接触窗口，第二重掺杂区域和金属层的多个沟槽。 沟槽形成在基部。 第一重掺杂区域分别在沟槽下方并且与具有轻掺杂区域的相应沟槽的底部间隔开。 体区域包围沟槽并且以预定距离远离第一重掺杂区域。 源极掺杂区域位于体区的上部。 接触窗口与基座的边缘相邻。 第二重掺杂区域在由用于电连接第二重掺杂区域的金属层填充的接触窗口的下方。

公开(公告)号：US08357972B2

公开(公告)日：2013-01-22

申请号：US13227472

申请日：2011-09-07

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

IPC分类号： H01L29/66

CPC分类号： H01L29/7811 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7803 ,  H01L29/7809

摘要： A semiconductor power device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. At least a recessed epitaxial structure is disposed within a cell region and the recessed epitaxial structure may be formed in a pillar or stripe shape. A first vertical diffusion region is disposed in the third semiconductor layer and the recessed epitaxial structure is surrounded by the first vertical diffusion region. A source conductor is disposed on the recessed epitaxial structure and a trench isolation is disposed within a junction termination region surrounding the cell region. In addition, the trench isolation includes a trench, a first insulating layer on an interior surface of the trench, and a conductive layer filled into the trench, wherein the source conductor connects electrically with the conductive layer.

摘要翻译： 半导体功率器件包括衬底，衬底上的第一半导体层，第一半导体层上的第二半导体层以及第二半导体层上的第三半导体层。 至少凹入的外延结构设置在单元区域内，并且凹入的外延结构可以形成为柱状或条形。 第一垂直扩散区域设置在第三半导体层中，并且凹入的外延结构被第一垂直扩散区域包围。 源极导体设置在凹陷的外延结构上，并且沟槽隔离设置在围绕电池区的连接终端区域内。 此外，沟槽隔离包括沟槽，在沟槽的内表面上的第一绝缘层和填充到沟槽中的导电层，其中源极导体与导电层电连接。

公开(公告)号：US08344451B2

公开(公告)日：2013-01-01

申请号：US11971152

申请日：2008-01-08

申请人： Mohamed N. Darwish

发明人： Mohamed N. Darwish

IPC分类号： H01L29/66

CPC分类号： H01L29/7802 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/2003 ,  H01L21/265 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823885 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66537 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835

摘要： A semiconductor device includes a semiconductor layer of a first conductivity type having a first surface and a second surface, a source region disposed on the first surface, a gate region disposed on the first surface adjacent the source region, and a drain region disposed on the first surface. The semiconductor device also includes a pair of charge control trenches disposed between the gate region and the drain region. Each of the pair of charge control trenches is characterized by a width and includes a first dielectric material disposed therein and a second material disposed internal to the first dielectric material. Additionally, a concentration of doping impurities present in the semiconductor layer of the first conductivity type and a distance between the pair of charge control trenches define an electrical characteristic of the semiconductor device that is independent of the width of each of the pair of charge control trenches.

摘要翻译： 半导体器件包括具有第一表面和第二表面的第一导电类型的半导体层，设置在第一表面上的源极区域，设置在与源极区域相邻的第一表面上的栅极区域和设置在源极区域上的漏极区域 第一表面。 半导体器件还包括设置在栅极区域和漏极区域之间的一对电荷控制沟槽。 一对电荷控制沟槽中的每一个的特征在于宽度并且包括设置在其中的第一电介质材料和设置在第一电介质材料内部的第二材料。 此外，存在于第一导电类型的半导体层中的掺杂杂质的浓度和一对电荷控制沟槽之间的距离限定了与一对电荷控制沟槽中的每一个的宽度无关的半导体器件的电特性 。