公开(公告)号：US09799549B2

公开(公告)日：2017-10-24

申请号：US14780467

申请日：2014-03-21

Applicant: Soitec

Inventor： Sebastien Kerdiles ,  Guillaume Chabanne ,  Francois Boedt ,  Aurelia Pierret ,  Xavier Schneider ,  Didier Landru

IPC: H01L21/762 ,  H01L21/02 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L21/76254 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/12 ,  H01L29/0649

Abstract: The disclosure relates to a process for manufacturing a composite structure, the process comprising the following steps: a) providing a donor substrate and a carrier substrate; b) forming a dielectric layer; c) forming a covering layer; d) forming a weakened zone in the donor substrate; e) joining the carrier substrate and the donor substrate via a contact surface having an outline; f) fracturing the donor substrate via the weakened zone, steps b) and e) being executed so that the outline is inscribed in the outline, and step c) being executed so that the covering layer covers the peripheral surface of the dielectric layer.

公开(公告)号：US20170253478A1

公开(公告)日：2017-09-07

申请号：US15449649

申请日：2017-03-03

Applicant: Soitec

Inventor： Bruno Ghyselen

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00801 ,  B81B7/0025 ,  B81B2203/0127 ,  B81B2207/015 ,  B81C1/00182 ,  B81C1/00626 ,  B81C2201/056

Abstract: A method for manufacturing a structure comprises a) providing a donor substrate comprising front and rear faces; b) providing a support substrate; c) forming an intermediate layer on the front face of the donor substrate or on the support substrate; d) assembling the donor and support substrates with the intermediate layer therebetween; e) thinning the rear face of the donor substrate to form a useful layer of a useful thickness having a first face disposed on the intermediate layer and a second free face; and wherein the donor substrate comprises a buried stop layer and a fine active layer having a first thickness less than the useful thickness, between the front face of the donor substrate and the stop layer; and after step e), removing, in first regions of the structure, a thick active layer delimited by the second free face of the useful layer and the stop layer.

公开(公告)号：US20170210617A1

公开(公告)日：2017-07-27

申请号：US15328371

申请日：2014-06-11

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ludovic Ecarnot

IPC: B81C1/00 ,  B81B1/00

Abstract: Methods of forming semiconductor structures comprising one or more cavities (106), which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate (100), providing a sacrificial material (110) within the one or more cavities, bonding a second substrate (120) over the a surface of the first substrate, forming one or more apertures (140) through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.

公开(公告)号：US20170168279A1

公开(公告)日：2017-06-15

申请号：US15374902

申请日：2016-12-09

Applicant: Soitec

Inventor： Olivier Pfersdorff

IPC: G02B21/00 ,  H04N5/225 ,  H01J37/28 ,  G02B21/10 ,  G02B21/36 ,  G02B21/26 ,  G06T7/00 ,  G06K9/46

CPC classification number: G02B21/0016 ,  G01B9/04 ,  G01B11/30 ,  G01N21/4738 ,  G01N21/8851 ,  G01N21/9501 ,  G01N2021/8822 ,  G01N2021/8874 ,  G01N2021/8928 ,  G02B21/10 ,  G02B21/26 ,  G02B21/365 ,  G06K9/4604 ,  G06T7/0004 ,  G06T2207/10056 ,  G06T2207/20076 ,  G06T2207/30148 ,  H01J37/28 ,  H04N5/2256

Abstract: A method for determining the size of a void-type defect in a top side of a structure comprising a top layer placed on a substrate, the defect being located in the top layer, includes introducing the structure into a reflected darkfield microscopy device in order to generate, from a light ray scattered by the top side, a defect-related first signal and a roughness-related second signal. The intensity of the roughness-related second signal is captured with a plurality of pixels. The intensity captured by each pixel is compared with the intensities captured by neighboring pixels. It is defined whether or not the pixel is contained in an abnormal zone. The standard deviation of the intensity values captured by the pixels of the abnormal zone is extracted, and the size of the void-type defect associated with the abnormal zone is determined from the extracted standard deviation. A new device may be used for carrying out such a method.

公开(公告)号：US09653536B2

公开(公告)日：2017-05-16

申请号：US14646642

申请日：2013-12-02

Applicant: Soitec

Inventor： Alexandre Chibko ,  Isabelle Bertrand ,  Sylvain Peru ,  Sothachett Van ,  Patrick Reynaud

IPC: H01L21/324 ,  H01L29/04 ,  H01L21/762 ,  H01L21/02 ,  H01L29/16 ,  H01L21/265

CPC classification number: H01L29/04 ,  H01L21/02263 ,  H01L21/02524 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/76254 ,  H01L29/16

Abstract: A method for fabricating a structure comprising, in succession, a support substrate, a dielectric layer, an active layer, a separator layer of polycrystalline silicon, comprising the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure, d) forming the separator layer on the support substrate, e) forming the dielectric layer, f) assembling the donor substrate and the support substrate, g) fracturing the donor substrate along the embrittlement area, h) subjecting the structure to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that step d) is executed in such a way that the polycrystalline silicon of the separator layer exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950° C. and less than 1200° C.

公开(公告)号：US09640664B2

公开(公告)日：2017-05-02

申请号：US14428561

申请日：2013-09-10

Applicant: Soitec

Inventor： Franz Hofmann

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/12 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L27/0214 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7855

Abstract: The present invention relates to a method for polarizing at least a first finfet transistor and a second finfet transistor, wherein the first finfet transistor has a fin width bigger than the fin width of the second finfet transistor, and both the first finfet transistor and the second finfet transistor have a back gate, and the method comprising applying the same first voltage on the back gate of the first finfet transistor and on the back gate of the second finfet transistor so as to reduce the spread between the off-current value of the first finfet transistor and the off-current value of the second finfet transistor.

公开(公告)号：US09634182B2

公开(公告)日：2017-04-25

申请号：US14991100

申请日：2016-01-08

Applicant: Soitec

Inventor： Jean-Philippe Debray ,  Chantal Arena ,  Heather McFavilen ,  Ding Ding ,  Li Huang

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L33/14 ,  H01L33/04 ,  H01L33/16

CPC classification number: H01L33/06 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/04 ,  H01L33/12 ,  H01L33/145 ,  H01L33/16 ,  H01L33/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

公开(公告)号：US09607879B2

公开(公告)日：2017-03-28

申请号：US14425205

申请日：2013-09-03

Applicant: Soitec

Inventor： Didier Landru

IPC: B23P19/00 ,  B23P19/02 ,  H01L21/762

CPC classification number: H01L21/76251 ,  H01L21/76254 ,  Y10T29/49822

Abstract: A process for fabrication of a structure includes assembling at least two substrates. At least one of these two substrates is intended to be used in electronics, optics, optoelectronics and/or photovoltaics. The structure includes at least two separation interfaces extending parallel to the main faces of the structure. The assembling process is carried out with a view to a separation of the structure along one interface selected from the interfaces, the separation being carried out by inserting a blade between the substrates and applying a parting force, via the blade. The interface chosen for the separation is formed so that it is more sensitive than the other interface(s) to stress corrosion. Separation occurs due to the combined action of the parting force and of a fluid capable of breaking siloxane (Si—O—Si) bonds present at the interface. A structure obtained by such a process may be separated along the chosen interface.

公开(公告)号：US09583341B2

公开(公告)日：2017-02-28

申请号：US14957133

申请日：2015-12-02

Applicant: Soitec

Inventor： Vivien Renauld ,  Monique Lecomte

IPC: H01L21/30 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/0254 ,  H01L21/02373 ,  H01L21/02488 ,  H01L21/02694 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76254 ,  H01L2221/68318 ,  H01L2221/6835 ,  H01L2221/68381

Abstract: A process for transferring a useful layer to a receiver substrate includes providing a donor substrate comprising an intermediate layer, a carrier substrate, and a useful layer. The intermediate layer is free of species liable to degas during a subsequent heat treatment, and is configured to become soft at a temperature. The receiver substrate and the donor substrate are assembled. An additional layer is provided between the receiver substrate and the carrier substrate that comprises chemical species that are susceptible to diffuse into the intermediate layer during the subsequent heat treatment so as to form a weak zone. The heat treatment is carried out on the receiver substrate and the donor substrate at a second temperature higher than the first temperature.

Abstract translation: 用于将有用层转移到接收器衬底的方法包括提供包括中间层，载体衬底和有用层的施主衬底。 中间层在随后的热处理期间不含易于脱气的物质，并且被配置为在温度下变软。 组装接收器基板和供体基板。 在接收器基板和载体基板之间提供了附加层，其包括在随后的热处理期间易于扩散到中间层中以形成弱区的化学物质。 在高于第一温度的第二温度下，在接收器基板和供体基板上进行热处理。

公开(公告)号：US09576798B2

公开(公告)日：2017-02-21

申请号：US14934567

申请日：2015-11-06

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Christophe Maleville

IPC: H01L21/8238 ,  H01L27/12 ,  H01L21/266 ,  H01L21/336 ,  H01L21/225 ,  H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L21/84 ,  H01L21/762 ,  H01L29/10

CPC classification number: H01L21/2253 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/76251 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/32 ,  H01L29/7849

Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括提供包括基底基板，在基底基板上方的应变应力层，表面半导体层和应力层与表面半导体层之间的电介质层的绝缘体上半导体 。 离子被注入或穿过应力层的第一区域，并且在应力层的第一区域上方的表面半导体层上形成附加的半导体材料。 在应力层的第一区域上方的表面半导体层的第一区域中的应变状态被改变，并且沟槽结构至少部分地形成到基底衬底中。 在应力层的第二区域上方的表面半导体层的第二区域中改变应变状态。 使用这种方法制造半导体结构。