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公开(公告)号:US20080246154A1
公开(公告)日:2008-10-09
申请号:US12138453
申请日:2008-06-13
申请人: Mou-Shiung Lin , Jin-Yuan Lee
发明人: Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号: H01L23/52
CPC分类号: H01L21/768 , H01L21/76804 , H01L21/76807 , H01L21/76838 , H01L23/522 , H01L23/5222 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L23/5228 , H01L23/525 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/60 , H01L24/11 , H01L24/12 , H01L27/0676 , H01L27/08 , H01L28/10 , H01L28/20 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/1148 , H01L2224/13099 , H01L2224/16225 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/12044 , H01L2924/14 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/351 , H01L2924/00
摘要: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.
摘要翻译: 本发明在完成的半导体晶片的顶部上添加一层或多层厚的聚合物电介质和一层或多层厚的宽金属线,后钝化。 厚的宽金属线路可用于长信号路径,也可用于电源总线或电源平面,时钟分配网络,关键信号和用于倒装芯片应用的I / O焊盘的重新分配。 光刻胶定义的电镀,溅射/蚀刻或双重和三重镶嵌技术用于形成金属线和通孔填充。
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公开(公告)号:US20080080113A1
公开(公告)日:2008-04-03
申请号:US11864938
申请日:2007-09-29
申请人: Mou-Shiung Lin , Jin-Yuan Lee , Chien-Kang Chou
发明人: Mou-Shiung Lin , Jin-Yuan Lee , Chien-Kang Chou
IPC分类号: H02H9/00
CPC分类号: H01L23/552 , H01L21/76816 , H01L21/76873 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L23/5329 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/48 , H01L24/73 , H01L27/0251 , H01L2224/02166 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05664 , H01L2224/1148 , H01L2224/13022 , H01L2224/13099 , H01L2224/16145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48664 , H01L2224/48724 , H01L2224/48747 , H01L2224/48764 , H01L2224/48824 , H01L2224/48847 , H01L2224/48864 , H01L2224/73257 , H01L2224/73265 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/01039 , H01L2924/00 , H01L2224/05552
摘要: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.
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公开(公告)号:US20080057703A1
公开(公告)日:2008-03-06
申请号:US11856083
申请日:2007-09-17
申请人: Mou-Shiung Lin , Jin-Yuan Lee
发明人: Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号: H01L23/532
CPC分类号: H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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公开(公告)号:US20080050909A1
公开(公告)日:2008-02-28
申请号:US11930682
申请日:2007-10-31
申请人: Mou-Shiung Lin , Jin-Yuan Lee
发明人: Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号: H01L21/4763
CPC分类号: H01L21/768 , H01L21/76804 , H01L21/76807 , H01L21/76838 , H01L23/522 , H01L23/5222 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L23/5228 , H01L23/525 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/60 , H01L24/11 , H01L24/12 , H01L27/0676 , H01L27/08 , H01L28/10 , H01L28/20 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/1148 , H01L2224/13099 , H01L2224/16225 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/12044 , H01L2924/14 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/351 , H01L2924/00
摘要: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.
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公开(公告)号:US20080045001A1
公开(公告)日:2008-02-21
申请号:US11856087
申请日:2007-09-17
申请人: Mou-Shiung Lin , Jin-Yuan Lee
发明人: Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号: H01L21/4763
CPC分类号: H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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公开(公告)号:US20080042296A1
公开(公告)日:2008-02-21
申请号:US11858905
申请日:2007-09-21
申请人: Mou-Shiung Lin , Jin-Yuan Lee
发明人: Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号: H01L23/52
CPC分类号: H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
摘要翻译: 提供了一种创建互连线的方法。 细线互连提供在已经在衬底的表面中或其上形成的半导体电路的第一绝缘层中。 钝化层沉积在电介质层上,在钝化层的表面上形成厚的第二层电介质。 在厚的第二层电介质中产生厚而宽的互连线。 也可以消除第一层电介质,在已经沉积在衬底的表面上的钝化层的表面上产生宽厚的互连网络。
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公开(公告)号:US20080042294A1
公开(公告)日:2008-02-21
申请号:US11856076
申请日:2007-09-17
申请人: Mou-Shiung Lin , Jin-Yuan Lee
发明人: Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号: H01L23/52
CPC分类号: H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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公开(公告)号:US20080042293A1
公开(公告)日:2008-02-21
申请号:US11856074
申请日:2007-09-17
申请人: Mou-Shiung Lin , Jin-Yuan Lee
发明人: Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号: H01L23/58
CPC分类号: H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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公开(公告)号:US20080042285A1
公开(公告)日:2008-02-21
申请号:US11856073
申请日:2007-09-17
申请人: Mou-Shiung Lin , Jin-Yuan Lee
发明人: Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号: H01L23/52
CPC分类号: H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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公开(公告)号:US20080042280A1
公开(公告)日:2008-02-21
申请号:US11769736
申请日:2007-06-28
申请人: Mou-Shiung Lin , Jin-Yuan Lee
发明人: Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号: H01L23/48
CPC分类号: H01L24/11 , H01L23/5227 , H01L23/53238 , H01L23/53252 , H01L24/05 , H01L24/06 , H01L24/12 , H01L24/16 , H01L24/28 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/94 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05084 , H01L2224/05553 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/1147 , H01L2224/1308 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/13171 , H01L2224/13173 , H01L2224/13176 , H01L2224/13181 , H01L2224/13183 , H01L2224/16 , H01L2224/29111 , H01L2224/2919 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48664 , H01L2224/48669 , H01L2224/48747 , H01L2224/48755 , H01L2224/48764 , H01L2224/48769 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/48864 , H01L2224/73204 , H01L2224/838 , H01L2224/85201 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/01327 , H01L2924/0133 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/0665 , H01L2924/0781 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/12044 , H01L2924/1305 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/30105 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/01032 , H01L2924/01031 , H01L2224/48869 , H01L2224/48744 , H01L2224/05552
摘要: A semiconductor chip structure includes a semiconductor substrate, an circuit structure, a passivation layer, a first adhesion/barrier layer, a metal cap and a metal layer. The semiconductor substrate has multiple electric devices located on a surface layer of a surface of the substrate. The circuit structure had multiple circuit layers electrically connecting with each other and electrically connecting with the electric devices. One of the circuit layers has multiple pads. The passivation layer is located on the circuit structure and has multiple openings penetrating through the passivation layer. The openings expose the pads. The first adhesion/barrier layer is over the pads and the passivation layer. The metal cap is located on the first adhesion/barrier layer and the passivation layer. The metal layer is on the metal layer.
摘要翻译: 半导体芯片结构包括半导体衬底,电路结构,钝化层,第一粘附/阻挡层,金属帽和金属层。 半导体衬底具有位于衬底表面的表面层上的多个电子器件。 电路结构具有彼此电连接并与电气装置电连接的多个电路层。 其中一个电路层具有多个焊盘。 钝化层位于电路结构上,具有贯穿钝化层的多个开口。 开口露出垫。 第一粘附/阻挡层在焊盘和钝化层之上。 金属盖位于第一粘附/阻挡层和钝化层上。 金属层在金属层上。
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