公开(公告)号：US08592995B2

公开(公告)日：2013-11-26

申请号：US12825822

申请日：2010-06-29

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/50

CPC classification number: H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/1308 ,  H01L2224/13084 ,  H01L2224/13147 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/16 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T428/24612 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/01015 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/1146

Abstract: A method and structure for good adhesion of Intermetallic Compounds (IMC) on Cu pillar bumps are provided. The method includes depositing Cu to form a Cu pillar layer, depositing a diffusion barrier layer on top of the Cu pillar layer, and depositing a Cu cap layer on top of the diffusion barrier layer, where an intermetallic compound (IMC) is formed among the diffusion barrier layer, the Cu cap layer, and a solder layer placed on top of the Cu cap layer. The IMC has good adhesion on the Cu pillar structure, the thickness of the IMC is controllable by the thickness of the Cu cap layer, and the diffusion barrier layer limits diffusion of Cu from the Cu pillar layer to the solder layer. The method can further include depositing a thin layer for wettability on top of the diffusion barrier layer prior to depositing the Cu cap layer.

Abstract translation: 提供了一种用于金属间化合物（IMC）对Cu柱凸块的良好粘附的方法和结构。 该方法包括沉积Cu以形成Cu柱层，在Cu柱层的顶部上沉积扩散阻挡层，并在扩散阻挡层的顶部上沉积Cu覆盖层，其中形成金属间化合物（IMC） 扩散阻挡层，Cu覆盖层和位于Cu覆盖层顶部的焊料层。 IMC对Cu柱结构具有良好的粘附性，IMC的厚度可由Cu覆盖层的厚度控制，扩散阻挡层限制Cu从Cu柱层到焊料层的扩散。 该方法可以进一步包括在沉积Cu覆盖层之前在扩散阻挡层的顶部沉积薄层以获得润湿性。

公开(公告)号：US08580683B2

公开(公告)日：2013-11-12

申请号：US13246556

申请日：2011-09-27

Applicant: Chung Yu Wang ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： Chung Yu Wang ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/28

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.

Abstract translation: 用于在晶片插入件上的模具上进行模制的方法和装置。 一种方法包括接收具有管芯侧面和相对侧的插入件组件，所述插入件组件包括安装在所述插入件的裸片侧上的两个或多个集成电路管芯，所述插入器组件具有形成在所述插入件的裸片侧上的两个或更多个集成 电路模具; 在所述两个或更多个集成电路管芯之间的空间之一中在所述插入器组件的管芯侧上安装至少一个应力释放特征; 以及使用模具化合物模制所述集成电路模具，围绕所述两个或更多个集成电路管芯的所述模具化合物以及所述至少一个应力释放特征。 公开了一种装置，其集成电路安装在插入件的裸片侧，集成电路之间的应力消除特征和集成电路上的模具化合物。

公开(公告)号：US20130249532A1

公开(公告)日：2013-09-26

申请号：US13429054

申请日：2012-03-23

Applicant: Jing-Cheng Lin ,  Szu Wei Lu

Inventor： Jing-Cheng Lin ,  Szu Wei Lu

IPC: G01R1/06 ,  H01L23/48

CPC classification number: H01L25/0655 ,  H01L21/563 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/11 ,  H01L2224/11002 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2224/83 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

公开(公告)号：US20130207306A1

公开(公告)日：2013-08-15

申请号：US13485307

申请日：2012-05-31

Applicant: Chih-Hao Chen ,  Hsien-Wen Liu ,  Yi-Lin Tsai ,  Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Chih-Hao Chen ,  Hsien-Wen Liu ,  Yi-Lin Tsai ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: B29C43/18 ,  H01L21/56

CPC classification number: B29C43/18 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/1531 ,  H01L2924/157 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature.

Abstract translation: 一种方法包括将聚合物模塑到包装部件上。 模制步骤包括在第一温度下进行的第一模塑阶段和在与第一温度不同的第二温度下进行的第二模塑阶段。

公开(公告)号：US20130199577A1

公开(公告)日：2013-08-08

申请号：US13369138

申请日：2012-02-08

Applicant: I-Ting Chen ,  Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： I-Ting Chen ,  Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: B08B7/04 ,  B08B5/00 ,  B08B3/08 ,  B08B3/02 ,  B08B3/12

CPC classification number: H01L21/02041 ,  H01L21/4864 ,  H01L21/67028 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/81911 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A flux residue cleaning system includes first and second immersion chambers, first and second spray chambers, and a drying chamber. The first immersion chamber softens an outer region of a flux residue formed around microbumps interposed between a wafer and a die when the wafer is immersed in a first chemical. The first spray chamber removes the outer region of the flux residue when the wafer is impinged upon by a first chemical spray in order to expose an inner region of the flux residue. The second immersion chamber softens the inner region of the flux residue when the wafer is immersed in a second chemical. The second spray chamber removes the inner region of the flux residue when the wafer is impinged upon by a second chemical spray in order to clean the wafer to a predetermined standard. The drying chamber dries the wafer.

Abstract translation: 助焊剂残渣清洁系统包括第一和第二浸没室，第一和第二喷雾室以及干燥室。 当晶片浸入第一化学品中时，第一浸入室软化在介于晶片和管芯之间的微胶片周围形成的焊剂残余物的外部区域。 当晶片通过第一化学喷雾冲击以便暴露焊剂残余物的内部区域时，第一喷雾室除去焊剂残余物的外部区域。 当晶片浸入第二种化学品中时，第二浸入室软化助焊剂残余物的内部区域。 当晶片被第二化学喷雾冲击时，第二喷雾室去除焊剂残余物的内部区域，以便将晶​​片清洁至预定的标准。 干燥室干燥晶片。

公开(公告)号：US08501590B2

公开(公告)日：2013-08-06

申请号：US13176606

申请日：2011-07-05

Applicant: Chung Yu Wang ,  Kung-Chen Yeh ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： Chung Yu Wang ,  Kung-Chen Yeh ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: H01L21/78

CPC classification number: H01L23/58 ,  H01L21/486 ,  H01L21/673 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: Methods and apparatus for performing dicing of die on wafer interposers. Methods are disclosed that include receiving an interposer assembly including one or more integrated circuit dies mounted on a die side of an interposer substrate and having scribe areas defined in spaces between the integrated circuit dies, the interposer having an opposite side for receiving external connectors; mounting the die side of the interposer assembly to a tape assembly, the tape assembly comprising an adhesive tape and preformed spacers disposed between and filling gaps between the integrated circuit dies; and sawing the interposer assembly by cutting the opposite side of the interposer in the scribe areas to make cuts through the interposer, the cuts separating the interposer into one or more die on wafer assemblies. Apparatuses are disclosed for use with the methods.

Abstract translation: 用于在晶片插入件上进行裸片切割的方法和装置。 公开了包括接收包括安装在插入器基板的裸片侧上的一个或多个集成电路管芯并且在集成电路管芯之间的空间中限定的划线区域的插入件组件的方法，所述插入器具有用于接收外部连接器的相对侧; 将所述插入器组件的模具侧安装到带组件上，所述带组件包括粘合带和设置在所述集成电路管芯之间的填充间隙之间的预成型间隔件; 以及通过在所述划线区域中切割所述插入件的相对侧来切割所述插入件组件，以切割所述插入件，所述切口将所述插入件分离成晶片组件上的一个或多个模具。 公开了与该方法一起使用的装置。

公开(公告)号：US20130187270A1

公开(公告)日：2013-07-25

申请号：US13452140

申请日：2012-04-20

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

IPC: H01L23/48

CPC classification number: H01L25/0655 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/742 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2223/54426 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/24991 ,  H01L2224/82005 ,  H01L2224/82106 ,  H01L2224/8213 ,  H01L2224/82132 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2924/00

Abstract: A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

Abstract translation: 封装包括在管芯的顶表面处具有导电焊盘的芯片，在导电焊盘上方并连接到导电焊盘的柱形凸块，以及重新分配线，并且连接到螺柱凸块。 电连接器在再分配线上电连接。

公开(公告)号：US20130140690A1

公开(公告)日：2013-06-06

申请号：US13311692

申请日：2011-12-06

Applicant: Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

Inventor： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/11011 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1405 ,  H01L2224/14104 ,  H01L2224/73204 ,  H01L2924/01028 ,  H01L2924/0132 ,  H01L2924/067 ,  H01L2924/0705 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

公开(公告)号：US20130134559A1

公开(公告)日：2013-05-30

申请号：US13397204

申请日：2012-02-15

Applicant: Jing-Cheng Lin ,  Hsin Chang ,  Shih Ting Lin

Inventor： Jing-Cheng Lin ,  Hsin Chang ,  Shih Ting Lin

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L23/28 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.

公开(公告)号：US20130119533A1

公开(公告)日：2013-05-16

申请号：US13297992

申请日：2011-11-16

Applicant: Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L21/78

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

Abstract translation: 晶片级封装包括结合在支撑晶片上的半导体管芯。 半导体管芯在其衬底上至少有一个台阶凹槽。 在半导体管芯和支撑晶片之间形成底部填充层。 此外，底部填充层的高度受到台阶凹槽的限制。 在晶片级封装的制造过程中，台阶凹槽有助于减小晶片级封装上的应力。