公开(公告)号：US08004083B2

公开(公告)日：2011-08-23

申请号：US11864927

申请日：2007-09-29

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Chien-Kang Chou

IPC分类号： H01L23/52

CPC分类号： H01L23/552 ,  H01L21/76816 ,  H01L21/76873 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L27/0251 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48764 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/01039 ,  H01L2924/00 ,  H01L2224/05552

摘要： An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.

公开(公告)号：US07999381B2

公开(公告)日：2011-08-16

申请号：US12353254

申请日：2009-01-13

申请人： Mou-Shiung Lin

发明人： Mou-Shiung Lin

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L25/50 ,  G01R31/2856 ,  G01R31/2884 ,  G01R31/31905 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry.

公开(公告)号：US07960269B2

公开(公告)日：2011-06-14

申请号：US11491117

申请日：2006-07-24

申请人： Hsin-Jung Lo ,  Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Hsin-Jung Lo ,  Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L21/2885 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76801 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48844 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/01004

摘要： A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.

摘要翻译： 一种用于制造电路部件的方法，包括在衬底上沉积第一金属层; 在所述第一金属层上形成第一图案界定层，所述第一图案限定层中的第一开口露出所述第一金属层; 在由所述第一开口暴露的所述第一金属层上沉积第二金属层; 去除所述第一图案限定层; 在所述第二金属层上形成第二图案限定层，在所述第二图案限定层中的第二开口暴露所述第二金属层; 在由所述第二开口暴露的所述第二金属层上沉积第三金属层; 去除所述第二图案限定层; 去除不在所述第二金属层下方的所述第一金属层; 以及在所述第二金属层上形成聚合物层，其中所述第三金属层用作结合到外部电路的金属凸块。

公开(公告)号：US07960212B2

公开(公告)日：2011-06-14

申请号：US11842957

申请日：2007-08-22

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC分类号： H01L21/00

CPC分类号： H01L25/50 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05624 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.

摘要翻译： 实现了制造芯片封装的方法。 在硅晶片上形成晶种层。 在种子层上形成光致抗蚀剂层，光致抗蚀剂层中的开口露出种子层。 在由开口暴露的种子层上形成第一焊料凸块。 去除光致抗蚀剂层。 不在第一焊料凸块下面的种子层被去除。 芯片上的第二焊料凸点与第一焊料凸块接合。

公开(公告)号：US07932172B2

公开(公告)日：2011-04-26

申请号：US12273548

申请日：2008-11-19

申请人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Hsin-Jung Lo

发明人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Hsin-Jung Lo

IPC分类号： H01L21/00

CPC分类号： H01L23/3192 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/19041

摘要： A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures, and a third metallization structure connecting said first and second metallization structures.

摘要翻译： 半导体芯片包括第一MOS器件，第二MOS器件，连接到所述第一MOS器件的第一金属化结构，连接到所述第二MOS器件的第二金属化结构，在所述第一和第二MOS器件上方的钝化层， 和第二金属化结构，以及连接所述第一和第二金属化结构的第三金属化结构。

公开(公告)号：US07923848B2

公开(公告)日：2011-04-12

申请号：US12353251

申请日：2009-01-13

申请人： Mou-Shiung Lin

发明人： Mou-Shiung Lin

IPC分类号： H01L23/52 ,  H01L29/40

CPC分类号： H01L25/50 ,  G01R31/2856 ,  G01R31/2884 ,  G01R31/31905 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry.

摘要翻译： 多集成电路芯片结构提供了结构的集成电路芯片之间的片上通信，没有ESD保护电路，没有输入/输出电路。 芯片间通信在集成电路芯片的内部电路之间。 该多集成电路芯片结构具有一个芯片间接口电路，用于选择性地将集成电路的内部电路连接到具有ESD保护电路和设计为在测试和老化过程期间与外部测试系统通信的输入/输出电路的测试接口电路。 多个互连的集成电路芯片结构具有安装到一个或多个第二集成电路芯片的第一集成电路芯片，以将集成电路芯片彼此物理和电连接。 第一集成电路芯片具有彼此连接的芯片间接口电路，以在每个集成电路芯片的内部电路连接到彼此的集成电路芯片或测试接口电路的内部电路之间选择性地通信，以在每个集成电路芯片的内部电路提供刺激和响应 测试程序。 模式选择器接收芯片外部的信号，以确定通信是否与其他连接的集成电路芯片中的一个或单芯片模式（例如与测试接口电路）通信。 ESD保护被添加到模式选择器电路。

公开(公告)号：US07919873B2

公开(公告)日：2011-04-05

申请号：US12269064

申请日：2008-11-12

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC分类号： H01L29/40

CPC分类号： H01L25/50 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05624 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.

公开(公告)号：US07915161B2

公开(公告)日：2011-03-29

申请号：US11856080

申请日：2007-09-17

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L21/4763

CPC分类号： H01L23/60 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/62 ,  H01L24/05 ,  H01L27/0248 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

公开(公告)号：US07906849B2

公开(公告)日：2011-03-15

申请号：US12032707

申请日：2008-02-18

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L28/10 ,  H01L21/768 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/60 ,  H01L24/02 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L27/0251 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/20 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/30105 ,  Y10T29/49124 ,  Y10T29/49204 ,  H01L2924/00

摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

公开(公告)号：US07884479B2

公开(公告)日：2011-02-08

申请号：US11839554

申请日：2007-08-16

申请人： Mou-Shiung Lin

发明人： Mou-Shiung Lin

IPC分类号： H01L23/48 ,  H01L23/522

CPC分类号： H01L24/12 ,  H01L21/768 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/60 ,  H01L24/11 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10T428/12542 ,  Y10T428/12993 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

摘要翻译： 将包含在半导体晶片内的集成电路紧密地互连到围绕半导体晶片的电路的方法。 通过有效利用聚酰亚胺或聚合物作为金属间电介质，将电互连长度保持在最小范围内，从而能够以更小的电路环境以非常小的集成电路集成在电路性能中的最小成本。