公开(公告)号：US20170133070A1

公开(公告)日：2017-05-11

申请号：US15390681

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G11C8/18 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10

CPC classification number: G11C8/18 ,  G06F13/161 ,  G06F13/1647 ,  G06F13/1657 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

公开(公告)号：US20160344577A1

公开(公告)日：2016-11-24

申请号：US15165134

申请日：2016-05-26

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Bruno W. Garlepp

IPC: H04L25/03 ,  H04L5/00 ,  H04J11/00

CPC classification number: H04L25/03057 ,  G01R31/31709 ,  G01R31/31711 ,  H04J11/0023 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L1/244 ,  H04L5/006 ,  H04L7/033 ,  H04L25/03146

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

Abstract translation: 描述了数字接收机边缘测试的方法和电路。 这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用于采用历史数据的接收机来减少符号间干扰（ISI）。 一些实施例允许独立于采样定时来调整反馈定时以测量某些形式的相位未对准和抖动的影响。

公开(公告)号：US09465961B2

公开(公告)日：2016-10-11

申请号：US14098628

申请日：2013-12-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brian S. Leibowitz ,  Pradeep Batra ,  Trung Am Diep

IPC: G06F12/14 ,  G06F21/85 ,  G06F21/78 ,  G09C1/00 ,  H04L9/06 ,  H04L9/12

CPC classification number: G06F21/85 ,  G06F21/78 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/065 ,  H04L9/12 ,  H04L2209/12 ,  H04L2209/56

Abstract: Described are systems and method for protecting data and instructions shared over a memory bus and stored in memory. Independent and separately timed stream ciphers for write and read channels allow timing variations between write and read transactions. Data and instructions can be separately encrypted prior to channel encryption to further secure the information. pad generators and related cryptographic circuits are shared for read and write data, and to secure addresses. The cryptographic circuits can support variable data widths, and in some embodiments memory devices incorporate security circuitry that can implement a shared-key algorithm using repurposed memory circuitry.

Abstract translation: 描述了用于保护在存储器总线上共享并存储在存储器中的数据和指令的系统和方法。 用于写入和读取通道的独立且单独定时的流密码允许写入和读取事务之间的时序变化。 数据和指令可以在通道加密之前单独加密，以进一步保护信息。 垫片发生器和相关的加密电路被共享用于读取和写入数据，并且保护地址。 加密电路可以支持可变数据宽度，并且在一些实施例中，存储器设备包括可以使用重用存储器电路来实现共享密钥算法的安全电路。

公开(公告)号：US09391816B2

公开(公告)日：2016-07-12

申请号：US14462561

申请日：2014-08-19

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

IPC: H03H7/30 ,  H04B1/10 ,  H04L27/06 ,  H04L7/00 ,  H04L25/03

CPC classification number: H04L25/03057 ,  G06F13/38 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

Abstract: A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

Abstract translation: 公开了一种方法。 该方法包括对数据信号的预期边沿时间具有电压值的数据信号进行采样。 产生第一个α值，并根据电压值生成第二个alpha值。 数据信号通过第一个alpha值进行调整，以得到第一个调整后的信号。 数据信号通过第二α值进行调整，以得到第二调整信号。 第一调整后的信号被采样以输出第一数据值，而第二调整信号被采样以输出第二数据值。 作为先前接收的数据值的函数，在第一数据值和第二数据值之间进行选择，以确定接收到的数据值。

公开(公告)号：US09262342B2

公开(公告)日：2016-02-16

申请号：US14133383

申请日：2013-12-18

Applicant: RAMBUS INC.

Inventor： Trung Am Diep ,  Pradeep Batra ,  Brian S. Leibowitz ,  Frederick A. Ware

IPC: G06F12/00 ,  G06F12/14 ,  G06F21/79 ,  G06F12/10

CPC classification number: G06F21/79 ,  G06F12/1009 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2221/2107 ,  H04L9/30

Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

Abstract translation: 存储器控制器至少部分地基于与页面帧相关联的帧密钥来加密页面帧的内容。 所述存储器控制器至少部分地基于与第一进程相关联的第一进程密钥来生成所述帧密钥的第一加密版本，其中所述帧密钥的所述第一加密版本被存储在与所述第一进程相关联的第一存储器表中。 所述存储器控制器至少部分地基于与第二进程相关联的第二进程密钥来生成所述帧密钥的第二加密版本，其中所述帧密钥的所述第二加密版本被存储在与所述第二进程相关联的第二存储器表中， 第一进程和第二进程分别使用帧密钥的第一加密版本和帧密钥的第二加密版本共享对页面帧的访问。

公开(公告)号：US20150332746A1

公开(公告)日：2015-11-19

申请号：US14813028

申请日：2015-07-29

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C8/12 ,  G11C8/18 ,  G11C5/02

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract translation: 描述了包括可编程命令和地址（CA）接口和/或可编程数据接口的存储器件。 在操作模式下，两个或多个CA接口可能处于活动状态。 在另一操作模式中，至少一个但不是全部的CA接口可能是活动的。 在操作模式下，所有数据接口都可能处于活动状态。 在另一种操作模式中，至少一个但不是全部的数据接口可能是活动的。 存储器装置可以包括用于选择：操作模式的电路; 操作模式中的子模式; 一个或多个CA接口作为活动CA接口; 来自多个活动CA接口的主CA接口; 和/或一个或多个数据接口作为活动数据接口。 电路可以基于一个或多个寄存器中的一个或多个位和/或在一个或多个引脚上接收到的一个或多个信号来执行这些选择。

公开(公告)号：US20150316975A1

公开(公告)日：2015-11-05

申请号：US14798050

申请日：2015-07-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Jared L. Zerbe ,  Brian S. Leibowitz

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/324 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2213/0038 ,  G11C5/14 ,  G11C5/148 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254

Abstract: A memory controller is transitioned to a low-power mode in which an active-mode resource required to transmit memory access commands to a memory device at a first command-signaling frequency is disabled. The memory controller transmits a first memory access command to the memory device using an alternative signaling resource during a transitional interval in which the active-mode resource is re-enabled.

Abstract translation: 存储器控制器转换到低功率模式，其中禁用以第一命令信令频率将存储器访问命令发送到存储器设备所需的主动模式资源。 存储器控制器在其中重新启用活动模式资源的过渡间隔期间使用替代信令资源向存储器设备发送第一存储器访问命令。

公开(公告)号：US20150309517A1

公开(公告)日：2015-10-29

申请号：US14699780

申请日：2015-04-29

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Michael D. Bucher ,  Lei Luo ,  Chaofeng Charlie Huang ,  Amir Amirkhany ,  Huy M. Nguyen ,  Hsuan-Jung (Bruce) Su ,  John Wilson

IPC: G05F1/46

CPC classification number: G05F1/462 ,  G11C5/147

Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.

Abstract translation: 集成电路包括用于提供调节电压的电压调节器和耦合到未终端传输线的数据输出。 该电路根据数据从电压调节器抽取可变量的功率。 电压调节器包括用于提供数据转变相关电流的第一电流产生电路。

公开(公告)号：US09110596B2

公开(公告)日：2015-08-18

申请号：US14445516

申请日：2014-07-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Jared L. Zerbe ,  Brian S. Leibowitz

IPC: G11C7/22 ,  G06F3/06 ,  G11C11/4072 ,  G11C11/4076 ,  G06F1/32 ,  G11C5/14

CPC classification number: G06F1/3275 ,  G06F1/324 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2213/0038 ,  G11C5/14 ,  G11C5/148 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254

Abstract: A memory device is transitioned to a low-power mode in which an active-mode resource required to receive memory access commands from a memory controller at a first command-signaling frequency of the memory device is disabled. A first memory access command, transmitted by the memory controller, is received within the memory device using an alternative signaling resource during a transitional interval in which the active-mode resource is re-enabled.

Abstract translation: 存储器件被转换到低功率模式，其中禁用在存储器设备的第一命令信号频率处从存储器控制器接收存储器访问命令所需的活动模式资源。 由存储器控制器发送的第一存储器访问命令在其中重新启用活动模式资源的过渡间隔期间使用备用信令资源在存储器设备内被接收。

公开(公告)号：US20150091617A1

公开(公告)日：2015-04-02

申请号：US14565802

申请日：2014-12-10

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

IPC: H03K5/13 ,  H03L7/16 ,  H03K5/00

CPC classification number: H03L7/16 ,  H03J2200/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/0995 ,  H03L7/24

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Abstract translation: 在第一时钟频率倍增器中，具有光谱交错锁定范围的多个注入锁定振荡器（ILO）并行操作，以实现基本上比孤立的国际劳工组织的输入频率范围更宽的集体输入频率范围。 在每个输入频率变化之后，可以根据一个或多个限定条件评估国际劳工组织输出时钟，以选择其中一个ILO作为最终的时钟源。 在第二个时钟倍频器中，灵活注入速率的注入锁定振荡器锁定到超谐波，次谐波或全频率注入脉冲，在不同的注入脉冲速率之间无缝转换，以实现宽的输入频率范围。 响应于输入时钟由第一和/或第二时钟频率乘法器影响的倍频因子在飞行中确定，然后与编程的（期望的）乘法因子进行比较，以在频率乘法器的不同分频实例之间进行选择 时钟。