公开(公告)号：US20060138618A1

公开(公告)日：2006-06-29

申请号：US11359002

申请日：2006-02-21

申请人： Vijayakumar RamachandraRao ,  Shriram Ramanathan

发明人： Vijayakumar RamachandraRao ,  Shriram Ramanathan

IPC分类号： H01L23/495

CPC分类号： H01L24/11 ,  H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08148 ,  H01L2224/13147 ,  H01L2224/16148 ,  H01L2224/81013 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2225/06513 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A method for wafer stacking employing substantially uniform copper structures is described herein.

摘要翻译： 本文描述了使用基本均匀的铜结构的晶片堆叠方法。

公开(公告)号：US20060003548A1

公开(公告)日：2006-01-05

申请号：US10898400

申请日：2004-07-23

申请人： Mauro Kobrinsky ,  Shriram Ramanathan ,  Scott List

发明人： Mauro Kobrinsky ,  Shriram Ramanathan ,  Scott List

IPC分类号： H01L21/30

CPC分类号： H01L21/67092 ,  H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/17 ,  H01L24/75 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05186 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/17 ,  H01L2224/75 ,  H01L2224/7511 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/81011 ,  H01L2224/81012 ,  H01L2224/81013 ,  H01L2224/81121 ,  H01L2224/81209 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/3511

摘要： The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

公开(公告)号：US20050079685A1

公开(公告)日：2005-04-14

申请号：US10683202

申请日：2003-10-09

申请人： Shriram Ramanathan ,  Grant Kloster ,  Patrick Morrow ,  Vijayakumar RamachandraRao ,  Scott List

发明人： Shriram Ramanathan ,  Grant Kloster ,  Patrick Morrow ,  Vijayakumar RamachandraRao ,  Scott List

IPC分类号： H01L21/46 ,  H01L23/485 ,  H01L25/065

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14

摘要： The invention provides a stacked wafer structure with decreased failures. In one embodiment, there is a barrier layer deposited on exposed surfaces of conductors that extend across a distance between first and second device structures. The barrier layer may prevent diffusion and electromigration of the conductor material, which may decrease incidences of shorts and voids in the stacked wafer structure.

摘要翻译： 本发明提供了具有降低的故障的堆叠晶片结构。 在一个实施例中，存在沉积在导体的暴露表面上的阻挡层，其延伸跨越第一和第二器件结构之间的距离。 阻挡层可以防止导体材料的扩散和电迁移，这可能降低层叠晶片结构中的短路和空隙的发生。

公开(公告)号：US20050025942A1

公开(公告)日：2005-02-03

申请号：US10631508

申请日：2003-07-31

申请人： Grant Kloster ,  Shriram Ramanathan ,  Chin-Chang Chen ,  Paul Fischer

发明人： Grant Kloster ,  Shriram Ramanathan ,  Chin-Chang Chen ,  Paul Fischer

IPC分类号： B32B3/00 ,  H01L21/762

CPC分类号： H01L21/76251 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/1146 ,  H01L2224/1148 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13578 ,  H01L2224/13624 ,  H01L2224/13657 ,  H01L2224/13666 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/13687 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81895 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10T29/49128 ,  Y10T428/24917 ,  H01L2924/00014

摘要： A method of bonding semiconductor devices is disclosed. The method comprises providing a first substrate having a first conductive interconnecting structure formed thereon and a second substrate having a second conductive interconnecting structure formed thereon. A first conductive passivation layer is selectively formed over exposed areas of the first conductive interconnecting structure. A second conductive passivation layer is selectively formed over exposed areas of the second conductive interconnecting structure. The first substrate and the second substrate are bonded together in such a way that the first conductive passivation layer bonds to the second conductive passivation layer to create a passivation-passivation interface.

摘要翻译： 公开了半导体器件的接合方法。 该方法包括提供其上形成有第一导电互连结构的第一基板和在其上形成有第二导电互连结构的第二基板。 在第一导电互连结构的暴露区域上选择性地形成第一导电钝化层。 在第二导电互连结构的暴露区域上有选择地形成第二导电钝化层。 第一衬底和第二衬底以这样的方式结合在一起，使得第一导电钝化层结合到第二导电钝化层以产生钝化钝化界面。

公开(公告)号：US20050003664A1

公开(公告)日：2005-01-06

申请号：US10861030

申请日：2004-06-04

申请人： Shriram Ramanathan ,  Sarah Kim

发明人： Shriram Ramanathan ,  Sarah Kim

IPC分类号： H01L21/60 ,  H01L21/98 ,  H01L25/065 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/12 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/8383 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00014

摘要： A method comprising: coating a conductive bump on a first substrate with a conductive material to form a coated conductive bump; coating a conductive bump on a second substrate with a conductive material to form a coated conductive bump; and bonding the coated conductive bump on the first substrate to the coated conductive bump on the second substrate to electrically connect the first substrate to the second substrate.

摘要翻译： 一种方法，包括：用导电材料涂覆在第一基板上的导电凸块以形成涂覆的导电凸块; 用导电材料在第二基板上涂覆导电凸块以形成涂覆的导电凸块; 以及将所述第一基板上的涂覆的导电凸块接合到所述第二基板上的所述涂覆的导电凸块上，以将所述第一基板电连接到所述第二基板。

公开(公告)号：US09755245B2

公开(公告)日：2017-09-05

申请号：US14113223

申请日：2011-04-25

申请人： Shriram Ramanathan ,  Laura Roen Stolar

发明人： Shriram Ramanathan ,  Laura Roen Stolar

IPC分类号： H01M4/90 ,  H01M8/1018 ,  B01J21/18 ,  B01J23/42 ,  B01J37/02 ,  B01J37/16 ,  H01M4/88 ,  H01M8/1007 ,  H01M4/92

CPC分类号： H01M4/9075 ,  B01J21/18 ,  B01J23/42 ,  B01J37/024 ,  B01J37/0242 ,  B01J37/16 ,  H01M4/8817 ,  H01M4/885 ,  H01M4/926 ,  H01M8/1007 ,  H01M2008/1095

摘要： A method of forming a catalyst material includes coating agglomerates of catalyst support particles with an ionomer material. After coating the agglomerates of catalyst support particles, a catalyst metal precursor is deposited by chemical infiltration onto peripheral surfaces of the agglomerates of catalyst support particles. The catalyst metal precursor is then chemically reduced to form catalyst metal on the peripheral surfaces of the agglomerates of catalyst support particles.

公开(公告)号：US09508675B2

公开(公告)日：2016-11-29

申请号：US13973975

申请日：2013-08-22

申请人： Daoqiang Lu ,  Chuan Hu ,  Gilroy J. Vandentop ,  Shriram Ramanathan ,  Rajashree Baskaran ,  Valery M. Dubin

发明人： Daoqiang Lu ,  Chuan Hu ,  Gilroy J. Vandentop ,  Shriram Ramanathan ,  Rajashree Baskaran ,  Valery M. Dubin

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/373 ,  H01L21/00

CPC分类号： H01L24/83 ,  H01L21/4871 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/19106 ,  H01L2924/00

摘要： A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.

公开(公告)号：US09343206B2

公开(公告)日：2016-05-17

申请号：US14373908

申请日：2013-02-06

申请人： You Zhou ,  Zheng Yang ,  Shriram Ramanathan

发明人： You Zhou ,  Zheng Yang ,  Shriram Ramanathan

IPC分类号： H01C7/10 ,  G11C11/56 ,  G11C13/00 ,  H01L45/00 ,  H01C7/18 ,  H01C17/06

CPC分类号： H01C7/10 ,  G11C11/5678 ,  G11C13/0004 ,  H01C7/18 ,  H01C17/06 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： A tunable resistance system includes a layer of a first functional material deposited on a component of the system. The first functional material undergoes a phase transition at a first critical voltage. An insulating layer is deposited upon the layer of first functional material. A layer of a second functional material deposited on the insulating layer. The second functional material undergoes a phase transition at a second critical voltage. The insulating layer is configured to induce a stress on the layer so as to change the first critical voltage. In this way, the resistance of the system is tunable, allowing the system to undergo multi-stage electrical switching of resistive states.

摘要翻译： 可调电阻系统包括沉积在系统的部件上的第一功能材料层。 第一功能材料在第一临界电压下经历相变。 绝缘层沉积在第一功能材料层上。 沉积在绝缘层上的第二功能材料层。 第二功能材料在第二临界电压下经历相变。 绝缘层被配置为在该层上引起应力以便改变第一临界电压。 以这种方式，系统的电阻是可调的，允许系统进行电阻状态的多级电气切换。

公开(公告)号：US20140375417A1

公开(公告)日：2014-12-25

申请号：US14373908

申请日：2013-02-06

申请人： You Zhou ,  Zheng Yang ,  Shriram Ramanathan

发明人： You Zhou ,  Zheng Yang ,  Shriram Ramanathan

IPC分类号： H01C7/10 ,  H01C17/06 ,  H01C7/18

CPC分类号： H01C7/10 ,  G11C11/5678 ,  G11C13/0004 ,  H01C7/18 ,  H01C17/06 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： A tunable resistance system includes a layer of a first functional material deposited on a component of the system. The first functional material undergoes a phase transition at a first critical voltage. An insulating layer is deposited upon the layer of first functional material. A layer of a second functional material deposited on the insulating layer. The second functional material undergoes a phase transition at a second critical voltage. The insulating layer is configured to induce a stress on the layer so as to change the first critical voltage. In this way, the resistance of the system is tunable, allowing the system to undergo multi-stage electrical switching of resistive states.

摘要翻译： 可调电阻系统包括沉积在系统的部件上的第一功能材料层。 第一功能材料在第一临界电压下经历相变。 绝缘层沉积在第一功能材料层上。 沉积在绝缘层上的第二功能材料层。 第二功能材料在第二临界电压下经历相变。 绝缘层被配置为在该层上引起应力以便改变第一临界电压。 以这种方式，系统的电阻是可调的，允许系统进行电阻状态的多级电气切换。

公开(公告)号：US20140051008A1

公开(公告)日：2014-02-20

申请号：US14113223

申请日：2011-04-25

申请人： Shriram Ramanathan ,  Laura Roen Stolar

发明人： Shriram Ramanathan ,  Laura Roen Stolar

IPC分类号： H01M4/90

CPC分类号： H01M4/9075 ,  B01J21/18 ,  B01J23/42 ,  B01J37/024 ,  B01J37/0242 ,  B01J37/16 ,  H01M4/8817 ,  H01M4/885 ,  H01M4/926 ,  H01M8/1007 ,  H01M2008/1095

摘要： A method of forming a catalyst material includes coating agglomerates of catalyst support particles with an ionomer material. After coating the agglomerates of catalyst support particles, a catalyst metal precursor is deposited by chemical infiltration onto peripheral surfaces of the agglomerates of catalyst support particles. The catalyst metal precursor is then chemically reduced to form catalyst metal on the peripheral surfaces of the agglomerates of catalyst support particles.

摘要翻译： 形成催化剂材料的方法包括用离聚物材料涂覆催化剂载体颗粒的附聚物。 在涂覆催化剂载体颗粒的附聚物之后，通过化学渗透将催化剂金属前体沉积在催化剂载体颗粒的附聚物的外围表面上。 然后催化剂金属前体被化学还原以在催化剂载体颗粒的附聚物的外围表面上形成催化剂金属。