公开(公告)号：US11894262B2

公开(公告)日：2024-02-06

申请号：US18087129

申请日：2022-12-22

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Rishabh Mehandru ,  Patrick Morrow

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L21/308

CPC分类号： H01L21/76289 ,  H01L21/76283 ,  H01L21/823481 ,  H01L27/1211 ,  H01L21/3086 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/1037 ,  H01L29/6656

摘要： Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

公开(公告)号：US11894236B2

公开(公告)日：2024-02-06

申请号：US17669555

申请日：2022-02-11

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Qiang Wan ,  Jun Xia ,  Kangshu Zhan ,  Tao Liu ,  Penghui Xu ,  Sen Li ,  Yanghao Liu

IPC分类号： H01L21/308 ,  H01L21/02 ,  H01L21/027 ,  H10B12/00

CPC分类号： H01L21/3086 ,  H01L21/0228 ,  H01L21/0273 ,  H10B12/03 ,  H10B12/30

摘要： A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.

公开(公告)号：US11881520B2

公开(公告)日：2024-01-23

申请号：US16647865

申请日：2017-12-29

申请人： Intel Corporation

发明人： Curtis Ward ,  Heidi M. Meyer ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H10B10/00 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

CPC分类号： H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

公开(公告)号：US11881409B2

公开(公告)日：2024-01-23

申请号：US17359669

申请日：2021-06-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Wei-Hao Huang ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Lung-En Kuo ,  Chia-Wei Hsu

IPC分类号： H01L21/308 ,  H01L21/306 ,  H01L21/027 ,  G03F1/38

CPC分类号： H01L21/3085 ,  H01L21/0274 ,  H01L21/30604 ,  G03F1/38

摘要： A method of cutting fins includes the following steps. A photomask including a snake-shape pattern is provided. A photoresist layer is formed over fins on a substrate. A photoresist pattern in the photoresist layer corresponding to the snake-shape pattern is formed by exposing and developing. The fins are cut by transferring the photoresist pattern and etching cut parts of the fins.

公开(公告)号：US11881408B2

公开(公告)日：2024-01-23

申请号：US17635081

申请日：2020-07-28

申请人： Paul Scherrer Institut

发明人： Lucia Romano ,  Konstantins Jefimovs ,  Matias Kagias ,  Joan Vila Comamala ,  Marco Stampanoni

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L31/028 ,  B81C1/00 ,  G02B5/18 ,  B82Y20/00 ,  B82Y40/00 ,  H01L31/18 ,  C09K13/08

CPC分类号： H01L21/30604 ,  B81C1/00619 ,  G02B5/1857 ,  H01L21/308 ,  H01L21/3085 ,  H01L21/3086 ,  H01L31/028 ,  B82Y20/00 ,  B82Y40/00 ,  C09K13/08 ,  G02B5/1838 ,  H01L31/1804 ,  Y02P70/50

摘要： Elements of photonic devices with high aspect ratio patterns are fabricated. A stabilizing catalyst that forms a stable metal-semiconductor alloy allows to etch a substrate in vertical direction even at very low oxidant concentration without external bias or magnetic field. A metal layer on the substrate reacts with the oxidant contained in air and catalyzes the semiconductor etching by the etchant. Air in continuous flow at the metal layer allows to maintain constant the oxidant concentration in proximity of the metal layer. The process can continue for a long time in order to form very high aspect ratio structures in the order of 10,000:1. Once the etched semiconductor structure is formed, the continuous air flow supports the reactant species diffusing through the etched semiconductor structure to maintain a uniform etching rate. The continuous air flow supports the diffusion of reaction by-products to avoid poisoning of the etching reaction.

公开(公告)号：US20240021433A1

公开(公告)日：2024-01-18

申请号：US17965727

申请日：2022-10-13

申请人： Applied Materials, Inc.

发明人： Scott FALK ,  Rajesh PRASAD ,  Sarah Michelle BOBEK ,  Harry WHITESELL ,  Kurt DECKER-LUCKE ,  Kyu-Ha SHIM ,  Adaeze OSONKIE ,  Tomohiko KITAJIMA

IPC分类号： H01L21/3115 ,  H01L21/311 ,  H01L21/266 ,  H01L21/308

CPC分类号： H01L21/31155 ,  H01L21/31116 ,  H01L21/266 ,  H01L21/3086

摘要： Methods for depositing a hardmask with ions implanted at different tilt angles are described herein. By performing ion implantation to dope an amorphous carbon hardmask at multiple tilt angles, an evenly distributed dopant profiled can be created. The implant tilt angle will determine a dopant profile that enhances the carbon hardmask hardness.

公开(公告)号：US20240004300A1

公开(公告)日：2024-01-04

申请号：US17855924

申请日：2022-07-01

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHIH-YING TSAI ,  JUI-SENG WANG ,  YI-YI CHEN

IPC分类号： G03F7/20 ,  H01L21/308 ,  H01L21/027 ,  G03F7/09

CPC分类号： G03F7/2047 ,  H01L21/3086 ,  G03F7/70466 ,  H01L21/0274 ,  G03F7/091

摘要： The present application provides a method of processing a substrate. The method of processing the substrate includes steps of forming a photosensitive layer on the substrate; performing a first exposure process to expose the photosensitive layer to actinic radiation through a first mask; performing a first developing process to remove portions of the photosensitive layer exposed to the actinic radiation and form an intermediate pattern; performing a second exposure process to expose the intermediate pattern to the actinic radiation through a second mask; performing a second developing process to remove portions of the intermediate pattern shielded from the actinic radiation and form a target pattern; and performing an etching process to remove portions of the substrate exposed by the target pattern.

公开(公告)号：US11862682B2

公开(公告)日：2024-01-02

申请号：US17511778

申请日：2021-10-27

申请人： Samsung Electronics Co., Ltd.

发明人： Jihye Yi ,  Moonseung Yang ,  Jungtaek Kim

IPC分类号： H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/265

CPC分类号： H01L29/1037 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/30604 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7848

摘要： A semiconductor device includes a substrate including an active region in a first direction, a plurality of channel layers on the active region and disposed in a direction perpendicular to an upper surface of the substrate, a gate electrode respectively surrounding the plurality of channel layers, and a source/drain structure respectively disposed on both sides of the gate electrode in the first direction and connected to each of the plurality of channel layers. The gate electrode extends in a second direction crossing the first direction. The gate electrode includes an overlapped portion in a region of the gate electrode on an uppermost channel layer of the plurality of channel layers. The overlapped portion of the gate electrode overlaps the source/drain structure in the first direction and has a side surface inclined toward the upper surface of the substrate.

公开(公告)号：US11854996B2

公开(公告)日：2023-12-26

申请号：US17239962

申请日：2021-04-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chiu-Hsiang Chen ,  Shih-Chun Huang ,  Yung-Sung Yen ,  Ru-Gun Liu

IPC分类号： H01L23/544 ,  H01L27/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/027 ,  G06F30/392

CPC分类号： H01L23/544 ,  G06F30/392 ,  H01L21/0274 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/0207 ,  H01L2223/54426

摘要： A method for fabricating a semiconductor device is provided. The method includes forming an alignment mark in a material layer, wherein the alignment mark has a step sidewall in the material layer, and the step sidewall of the alignment mark has a floor surface portion; forming a feature material over the material layer; and performing a planarization process at least on the feature material, wherein the planarization process stops at a level higher than the floor surface portion of the step sidewall of the alignment mark.

公开(公告)号：US11854818B2

公开(公告)日：2023-12-26

申请号：US17307813

申请日：2021-05-04

申请人： Applied Materials, Inc.

发明人： Tassie Andersen ,  Shurong Liang

IPC分类号： H01L21/308 ,  H01L21/3065

CPC分类号： H01L21/3085 ,  H01L21/3065

摘要： Methods of processing a feature on a semiconductor workpiece are disclosed. The method is performed after features have been created on the workpiece. An etching species may be directed toward the workpiece at a non-zero tilt angle. In certain embodiments, the tilt angle may be 30° or more. Further, the etching species may also be directed with a non-zero twist angle. In certain embodiments, the etching species may sputter material from the features, while in other embodiments, the etching species may be a chemically reactive species. By adjusting the tilt and twist angles, as well as the flow rate of the etching species and the exposure time, the LER and LWR of a feature may be reduced with minimal impact of the CD of the feature.