公开(公告)号：US20110065238A1

公开(公告)日：2011-03-17

申请号：US12769725

申请日：2010-04-29

Applicant: Wen-Chih CHIOU ,  Weng-Jin WU ,  Shau-Lin SHUE

Inventor： Wen-Chih CHIOU ,  Weng-Jin WU ,  Shau-Lin SHUE

IPC: H01L21/50 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/81 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A wafer is attached to a carrier by using an adhesive layer, and a portion of the adhesive layer is exposed adjacent to an edge of the wafer. After thinning the wafer, a protection layer is provided to cover the exposed portion of the adhesive layer. A plurality of dies is bonded onto the thinned wafer, and then the thinned wafer and the dies are encapsulated with a molding compound.

Abstract translation: 通过使用粘合剂层将晶片附接到载体，并且粘合剂层的一部分暴露于晶片的边缘附近。 在使晶片变薄之后，提供保护层以覆盖粘合剂层的暴露部分。 将多个模具结合到薄的晶片上，然后用模塑料封装薄化的晶片和模具。

公开(公告)号：US07897481B2

公开(公告)日：2011-03-01

申请号：US12329304

申请日：2008-12-05

Applicant: Wen-Chih Chiou ,  Weng-Jin Wu ,  Chen-Hua Yu

Inventor： Wen-Chih Chiou ,  Weng-Jin Wu ,  Chen-Hua Yu

IPC: H01L21/98

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A method of forming integrated circuits includes providing a wafer that includes a plurality of dies; aligning a first top die to a first bottom die in the wafer; recording a first destination position of the first top die after the first top die is aligned to the first bottom die; bonding the first top die onto the first bottom die; calculating a second destination position of a second top die using the first destination position; moving the second top die to the second destination position; and bonding the second top die onto a second bottom die without any additional alignment action.

Abstract translation: 一种形成集成电路的方法包括提供包括多个管芯的晶片; 将第一顶模与所述晶片中的第一底模对准; 在所述第一顶模与所述第一底模对准之后，记录所述第一顶模的第一目的位置; 将第一顶模连接到第一底模上; 使用所述第一目的地位置计算第二顶模的第二目的位置; 将第二顶部模具移动到第二目的地位置; 以及将所述第二顶模连接到第二底模上而没有任何附加的对准作用。

公开(公告)号：US20100327463A1

公开(公告)日：2010-12-30

申请号：US12878060

申请日：2010-09-09

Applicant: Chen-Hua YU ,  Wen-Chih CHIOU ,  Weng-Jin WU ,  Jean WANG

Inventor： Chen-Hua YU ,  Wen-Chih CHIOU ,  Weng-Jin WU ,  Jean WANG

IPC: H01L25/07

CPC classification number: H01L21/76898 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/14051 ,  H01L2224/14135 ,  H01L2224/14155 ,  H01L2224/14179 ,  H01L2224/17517 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29035 ,  H01L2224/29075 ,  H01L2224/29116 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/29169 ,  H01L2224/29184 ,  H01L2224/29186 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81193 ,  H01L2224/83193 ,  H01L2224/9202 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12041 ,  H01L2924/14 ,  Y10S438/926 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/049 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A stacked structure includes a first substrate bonded to a second substrate such that a first pad structure of the first substrate contacts a second pad structure of the second substrate. A transistor gate is formed over the second substrate, and a first conductive structure extends through the second substrate and has a top surface that is substantially planar with a top surface of the second substrate. An interlayer dielectric (ILD) layer is disposed over the transistor gate, and a passivation layer is disposed over the ILD layer and includes a second pad structure that makes electrical contact with the second conductive structure. The ILD layer includes at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate. A second conductive structure is disposed in the ILD layer and is at least partially disposed over a surface of the first conductive structure.

Abstract translation: 层叠结构包括结合到第二基板的第一基板，使得第一基板的第一焊盘结构接触第二基板的第二焊盘结构。 晶体管栅极形成在第二衬底上，并且第一导电结构延伸穿过第二衬底并且具有与第二衬底的顶表面基本平坦的顶表面。 在晶体管栅极上设置层间绝缘层（ILD）层，钝化层设置在ILD层之上，并且包括与第二导电结构电接触的第二焊盘结构。 ILD层包括延伸穿过ILD层并与晶体管栅极电接触的至少一个接触结构。 第二导电结构设置在ILD层中并且至少部分地设置在第一导电结构的表面上。

公开(公告)号：US20100237502A1

公开(公告)日：2010-09-23

申请号：US12631172

申请日：2009-12-04

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/76847 ,  H01L21/76898 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of the opening. A seed layer is formed over the barrier layer, and the TSV opening is filled with a conductive filler. Another embodiment includes a barrier layer formed using atomic layer deposition.

Abstract translation: 公开了一种用于保护硅通孔（TSV）的系统和方法。 一个实施例包括在衬底中形成开口。 在开口中形成衬垫，并且沿着开口的侧壁和底部形成包含碳或氟的阻挡层。 在阻挡层上形成种子层，并且用导电填料填充TSV开口。 另一实施例包括使用原子层沉积形成的阻挡层。

公开(公告)号：US20100122456A1

公开(公告)日：2010-05-20

申请号：US12272404

申请日：2008-11-17

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

IPC: H05K3/30

CPC classification number: H01L24/74 ,  H01L24/75 ,  H01L24/80 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/74 ,  H01L2224/75102 ,  H01L2224/75251 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75705 ,  H01L2224/75753 ,  H01L2224/75901 ,  H01L2224/80055 ,  H01L2224/80075 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83055 ,  H01L2224/83075 ,  H01L2224/83801 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49135 ,  H01L2924/00

Abstract: A method for bonding includes providing a first die and a second die; scanning at least one of the first die and the second die to determine thickness variations of the at least one of the first die and the second die; placing the second die facing the first die with a first surface of the first die facing a second surface of the second die; aligning the first surface and the second surface parallel to each other using the thickness variations; and bonding the second die onto the first die. The step of aligning the first surface and the second surface includes tilting one of the first die and the second die.

Abstract translation: 一种用于接合的方法包括提供第一模具和第二模具; 扫描第一管芯和第二管芯中的至少一个，以确定第一管芯和第二管芯中的至少一个的厚度变化; 将所述第二模具面向所述第一模具，所述第一模具的第一表面面向所述第二模具的第二表面; 使用厚度变化使第一表面和第二表面彼此平行; 以及将所述第二模具接合到所述第一模具上。 对准第一表面和第二表面的步骤包括倾斜第一模具和第二模具中的一个。

公开(公告)号：US20090311829A1

公开(公告)日：2009-12-17

申请号：US12140695

申请日：2008-06-17

Applicant: Ku-Feng Yang ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Ming-Chung Sung

Inventor： Ku-Feng Yang ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Ming-Chung Sung

IPC: H01L21/48 ,  H01L21/44

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/48

Abstract: An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die.

Abstract translation: 集成电路结构包括底部半导体芯片; 顶部芯片结合到底部半导体芯片上; 围绕底模和底部半导体芯片的保护材料; 以及在顶模和保护材料上方的平面介电层。 保护材料具有与顶模的顶表面平齐的顶表面。

公开(公告)号：US20090224371A1

公开(公告)日：2009-09-10

申请号：US12043023

申请日：2008-03-05

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3171 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/81054 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/8192 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/01039 ,  H01L2924/00

Abstract: The formation of bonding pad protective layer over exposed bonding pad materials between stacked integrated circuit (IC) dies or wafers is described in preferred embodiments in which the bonding pad protective layer is formed in the integrated process of forming wafer bonding pads. The bonding pad protective layer prevents the exposed bonding pad materials from oxidation and corrosion in open-air or other harsh environments. By providing a bonding pad protective layer on exposed bonding pad materials, significant product reliability improvement is expected on ICs having a three-dimensional “stacked-die” configuration.

Abstract translation: 在堆叠的集成电路（IC）晶片之间的暴露的焊盘材料上的焊盘保护层的形成在其中在形成晶片接合焊盘的集成工艺中形成焊盘保护层的优选实施例中进行了描述。 接合焊盘保护层防止暴露的焊盘材料在露天或其他恶劣环境中受到氧化和腐蚀。 通过在暴露的焊盘材料上提供焊盘保护层，预期在具有三维“堆叠 - 裸片”结构的IC上可以显着提高产品的可靠性。

公开(公告)号：US20080191310A1

公开(公告)日：2008-08-14

申请号：US11705614

申请日：2007-02-12

Applicant: Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

Inventor： Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L29/00 ,  H01L21/762

CPC classification number: H01L21/8221 ,  H01L21/2007 ,  H01L27/0688

Abstract: A three-dimensional (3D) integrated circuit structure includes a first wafer and a second wafer, each comprising a substrate having devices formed thereon and an interconnect structure over the substrate; a composite layer comprising a first dielectric layer bonded to a second dielectric layer, wherein the composite layer is bonded to the first and the second wafers; a first plurality of openings extending from an interface of the first and the second dielectric layers into the first dielectric layer, wherein each opening of the first plurality of openings is in scribe lines of the first wafer; and vias connecting devices in the first and the second wafers.

Abstract translation: 三维（3D）集成电路结构包括第一晶片和第二晶片，每个晶片包括其上形成有器件的衬底和在衬底上的互连结构; 复合层，其包括结合到第二介电层的第一介电层，其中所述复合层结合到所述第一和第二晶片; 第一多个开口，从第一和第二介电层的界面延伸到第一介电层中，其中第一多个开口的每个开口处于第一晶片的划线中; 以及连接第一和第二晶片中的器件的通孔。

公开(公告)号：US20080142990A1

公开(公告)日：2008-06-19

申请号：US11641324

申请日：2006-12-19

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Hung-Jung Tu ,  Ku-Feng Yang

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Hung-Jung Tu ,  Ku-Feng Yang

IPC: H01L23/538 ,  H01L21/56

CPC classification number: H01L21/8221 ,  H01L21/76898 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10S148/164 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/013

Abstract: A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.

Abstract translation: 半导体结构包括第一裸片，其包括第一衬底和第一衬底上的第一焊盘，第二裸片，具有与第一表面相对的第一表面和第二表面，其中第二裸片堆叠在第一裸片上， 层，其具有在第二管芯的侧壁上的垂直部分，以及在第一管芯上延伸的水平部分。

公开(公告)号：US07385283B2

公开(公告)日：2008-06-10

申请号：US11426734

申请日：2006-06-27

Applicant: Weng-Jin Wu ,  Wen-Chih Chiou

Inventor： Weng-Jin Wu ,  Wen-Chih Chiou

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L21/6835 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/83

Abstract: A three dimensional integrated circuit structure includes at least first and second devices, each device comprising a substrate and a device layer formed over the substrate, the first and second devices being bonded together in a stack, wherein the bond between the first and second devices comprises a metal-to-metal bond and a non-metal-to-non-metal bond.

Abstract translation: 三维集成电路结构包括至少第一和第二器件，每个器件包括衬底和形成在衬底上的器件层，第一和第二器件以堆叠结合在一起，其中第一和第二器件之间的结合包括 金属对金属键和非金属对非金属键。