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81.发明授权公开(公告)号：US09530748B2
公开(公告)日：2016-12-27
申请号：US14604545
申请日：2015-01-23
Applicant: Micron Technology, Inc.
Inventor： Choon Kuan Lee , Chin Hui Chong , David J. Corisis
IPC: H01L23/02 , H01L23/00 , H01L21/768 , H01L23/31 , H01L23/48 , H01L25/065 , H01L25/00
CPC classification number: H01L24/29 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/50 , H01L2224/06181 , H01L2224/16145 , H01L2224/29005 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06572 , H01L2924/00014 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.
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82.发明申请公开(公告)号：US20160358831A1
公开(公告)日：2016-12-08
申请号：US15144699
申请日：2016-05-02
Applicant: Micron Technology, Inc.
Inventor： David J. Corisis , Chin Hui Chong , Choon Kuan Lee
IPC: H01L23/053 , H01L25/065 , H01L23/538 , H01L23/00 , H01L23/31 , H01L23/498
CPC classification number: H01L23/053 , H01L21/56 , H01L21/561 , H01L22/10 , H01L23/3128 , H01L23/3178 , H01L23/49805 , H01L23/49861 , H01L23/5389 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/45 , H01L24/46 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/074 , H01L25/105 , H01L25/117 , H01L2224/05554 , H01L2224/16 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/484 , H01L2224/48599 , H01L2224/4911 , H01L2224/4912 , H01L2224/49171 , H01L2224/73265 , H01L2224/81 , H01L2224/85 , H01L2224/97 , H01L2225/06503 , H01L2225/06506 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06548 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2225/1064 , H01L2225/1088 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/12042 , H01L2924/14 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/1627 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
Abstract: Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.
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83.发明申请NOVEL BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME 审中-公开用于集成电路装置的新型建立包装及其制造方法公开(公告)号：US20160247737A1
公开(公告)日：2016-08-25
申请号：US15145760
申请日：2016-05-03
Applicant: Micron Technology, Inc.
Inventor： Hong Wan Ng , Choon Kuan Lee , David J. Corisis , Chin Hui Chong
CPC classification number: H01L23/18 , H01L21/56 , H01L21/565 , H01L21/568 , H01L21/7806 , H01L23/3107 , H01L23/373 , H01L24/13 , H01L24/19 , H01L24/95 , H01L24/96 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05568 , H01L2224/05624 , H01L2224/05644 , H01L2224/12105 , H01L2924/01029 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/3512 , H01L2924/00 , H01L2924/00014
Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.
Abstract translation: 公开了一种在一个说明性示例中包括具有活性表面的集成电路管芯和围绕模具的周边延伸的成型体的模制器件，所述模制体具有位于模具的有效表面的一部分上方的唇缘 。 另一示例性实例包括具有活性表面的集成电路管芯，围绕管芯的周边延伸的成型体和围绕与管芯的有效表面相邻的管芯周边的至少一部分周围形成的CTE缓冲材料，其中， CTE缓冲材料位于模具的一部分和模制体的一部分之间，并且其中CTE缓冲材料的热膨胀系数为模具的热膨胀系数的中间系数和模制的热膨胀系数 身体。
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公开(公告)号：US20160172349A1
公开(公告)日：2016-06-16
申请号：US15050231
申请日：2016-02-22
Applicant: Micron Technology, Inc.
Inventor： Seng Kim Dalson Ye , Chin Hui Chong
CPC classification number: H01L25/0657 , H01L21/563 , H01L23/13 , H01L23/3114 , H01L24/48 , H01L25/00 , H01L25/043 , H01L25/074 , H01L25/0756 , H01L25/10 , H01L25/105 , H01L25/117 , H01L25/50 , H01L2224/06135 , H01L2224/06136 , H01L2224/32145 , H01L2224/32225 , H01L2224/4382 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06555 , H01L2225/06572 , H01L2225/06575 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/01078 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599 , H01L2224/85399
Abstract: A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.
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公开(公告)号：US09362260B2
公开(公告)日：2016-06-07
申请号：US14629094
申请日：2015-02-23
Applicant: Micron Technology, Inc.
Inventor： David J. Corisis , Chin Hui Chong , Choon Kuan Lee
IPC: H01L25/10 , H01L23/13 , H01L23/24 , H01L23/495 , H01L23/00
CPC classification number: H01L25/105 , H01L23/13 , H01L23/24 , H01L23/49517 , H01L23/49541 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48227 , H01L2224/49171 , H01L2225/1029 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/10161 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged integrated circuit device and a plurality of planar conductive members conductively coupling the first and second packaged integrated circuit devices to one another. A method is also disclosed which includes conductively coupling a plurality of extensions on a leadframe to each of a pair of stacked packaged integrated circuit devices and cutting the leadframe to singulate the extensions from one another.
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Patent Agency Ranking
公开(公告)号：US09299684B2
公开(公告)日：2016-03-29
申请号：US14011138
申请日：2013-08-27
Applicant: Micron Technology, Inc.
Inventor： Seng Kim Dalson Ye , Chin Hui Chong
CPC classification number: H01L25/0657 , H01L21/563 , H01L23/13 , H01L23/3114 , H01L24/48 , H01L25/00 , H01L25/043 , H01L25/074 , H01L25/0756 , H01L25/10 , H01L25/105 , H01L25/117 , H01L25/50 , H01L2224/06135 , H01L2224/06136 , H01L2224/32145 , H01L2224/32225 , H01L2224/4382 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06555 , H01L2225/06572 , H01L2225/06575 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/01078 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599 , H01L2224/85399
Abstract: A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.
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87.发明申请ELECTRONIC DEVICE ASSEMBLIES INCLUDING CONDUCTIVE VIAS HAVING TWO OR MORE CONDUCTIVE ELEMENTS 审中-公开电子设备组件，包括具有两个或更多导电元件的导电VIAS公开(公告)号：US20150319860A1
公开(公告)日：2015-11-05
申请号：US14797721
申请日：2015-07-13
Applicant: Micron Technology, Inc.
Inventor： David J. Corisis , Choon Kuan Lee , Chin Hui Chong
CPC classification number: H05K1/115 , G01R31/026 , G06F1/16 , H01L21/486 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L23/66 , H01L2223/6616 , H01L2223/6638 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0221 , H05K1/0245 , H05K1/0251 , H05K1/0296 , H05K1/18 , H05K3/42 , H05K3/429 , H05K2201/09236 , H05K2201/09672 , H05K2201/09809 , Y10T29/49165 , H01L2924/00
Abstract: Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.
Abstract translation: 电子器件包括具有在衬底中或衬底上延伸的第一和第二对导电迹线的衬底。 第一导电互连构件延伸穿过衬底中的孔并且与第一和第二对中的每一个的第一迹线电连通，而第二导电互连构件延伸穿过孔并与第一导电互连构件中的每一个的第二迹线电连通 和第二对。 第一和第二互连构件彼此间隔开距离，该距离基本上等于分隔每对导电迹线的距离。 电子设备组件包括被配置为通过导电结构将差分信号传输到接收设备的发送设备。 导电结构包括第一和第二对导电迹线，其中第一和第二互连构件之间提供电连通。
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88.发明申请公开(公告)号：US20150171061A1
公开(公告)日：2015-06-18
申请号：US14629094
申请日：2015-02-23
Applicant: Micron Technology, Inc.
Inventor： David J. Corisis , Chin Hui Chong , Choon Kuan Lee
IPC: H01L25/10 , H01L23/495
CPC classification number: H01L25/105 , H01L23/13 , H01L23/24 , H01L23/49517 , H01L23/49541 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48227 , H01L2224/49171 , H01L2225/1029 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/10161 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged integrated circuit device and a plurality of planar conductive members conductively coupling the first and second packaged integrated circuit devices to one another. A method is also disclosed which includes conductively coupling a plurality of extensions on a leadframe to each of a pair of stacked packaged integrated circuit devices and cutting the leadframe to singulate the extensions from one another.
Abstract translation: 公开了一种装置，其包括第一封装集成电路器件，位于第一封装集成电路器件上方的第二封装集成电路器件以及将第一和第二封装集成电路器件彼此导电耦合的多个平面导电元件。 还公开了一种方法，其包括将引线框上的多个延伸部导电地耦合到一对堆叠封装的集成电路器件中的每一个并切割引线框架以将延伸部彼此分离。
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公开(公告)号：US20150137364A1
公开(公告)日：2015-05-21
申请号：US14470831
申请日：2014-08-27
Applicant: Micron Technology, Inc.
Inventor： Seng Kim Dalson Ye , Chin Hui Chong , Choon Kuan Lee , Wang Lai Lee , Roslan Bin Said
CPC classification number: H01L23/3128 , H01L21/561 , H01L23/49833 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/97 , H01L25/00 , H01L25/105 , H01L25/117 , H01L25/50 , H01L2224/0401 , H01L2224/05599 , H01L2224/06136 , H01L2224/16055 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2224/83 , H01L2224/85 , H01L2224/92147 , H01L2224/92247 , H01L2224/97 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/0102 , H01L2924/01033 , H01L2924/01047 , H01L2924/01052 , H01L2924/0106 , H01L2924/01074 , H01L2924/01078 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/30105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
Abstract: Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.
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90.发明申请公开(公告)号：US20150130081A1
公开(公告)日：2015-05-14
申请号：US14604545
申请日：2015-01-23
Applicant: Micron Technology, Inc.
Inventor： Choon Kuan Lee , Chin Hui Chong , David J. Corisis
CPC classification number: H01L24/29 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/50 , H01L2224/06181 , H01L2224/16145 , H01L2224/29005 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06572 , H01L2924/00014 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.
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