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131 records (took 0.029 seconds)

    Multi-chip integrated fan-out package
    82.
    发明授权
    Multi-chip integrated fan-out package 有权

    公开(公告)号：US12148728B2

    公开(公告)日：2024-11-19

    申请号：US17646778

    申请日：2022-01-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jie Chen ,  Hsien-Wei Chen

    IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10 ,  H01L21/3105 ,  H01L23/31

    Abstract: A method includes surrounding a die and a conductive pillar proximate the die with a molding material, where the die and the conductive pillar are disposed over a first side of a first redistribution structure, where a second side of the first redistribution structure opposing the first side is attached to a first carrier; bonding conductive pads disposed on a first surface of a pre-made second redistribution structure to the die and to the conductive pillar, where a second surface of the pre-made second redistribution structure opposing the first surface is attached to a second carrier; after bonding the conductive pads, removing the second carrier to expose conductive features of the pre-made second redistribution structure proximate the second surface; and forming conductive bumps over and electrically coupled to the conductive features of the pre-made second redistribution structure.

    Semiconductor package and manufacturing method thereof
    87.
    发明授权
    Semiconductor package and manufacturing method thereof 有权

    公开(公告)号：US11609391B2

    公开(公告)日：2023-03-21

    申请号：US16877498

    申请日：2020-05-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

    IPC: H01L23/498 ,  H01L21/48 ,  G02B6/42

    Abstract: A semiconductor package includes a semiconductor die, a device layer, an insulator layer, a buffer layer, and connective terminals. The device layer is stacked over the semiconductor die. The device layer includes an edge coupler located at an edge of the semiconductor package and a waveguide connected to the edge coupler. The insulator layer is stacked over the device layer and includes a first dielectric material. The buffer layer is stacked over the insulator layer. The buffer layer includes a second dielectric material. The connective terminals are disposed on the buffer layer and reach the insulator layer through contact openings of the buffer layer.

    SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME
    89.
    发明申请
    SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20220223553A1

    公开(公告)日：2022-07-14

    申请号：US17315487

    申请日：2021-05-10

    Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

    Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Sung-Feng Yeh ,  Jie Chen

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

    Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

    STRUCTURE AND METHOD FOR FORMING INTEGRATED HIGH DENSITY MIM CAPACITOR
    90.
    发明申请
    STRUCTURE AND METHOD FOR FORMING INTEGRATED HIGH DENSITY MIM CAPACITOR 有权

    公开(公告)号：US20210391413A1

    公开(公告)日：2021-12-16

    申请号：US16901912

    申请日：2020-06-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Jie Chen ,  Ming-Fa Chen

    IPC: H01L49/02 ,  H01L21/768 ,  H01G4/30 ,  H01L23/522

    Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

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