公开(公告)号：US5626771A

公开(公告)日：1997-05-06

申请号：US470270

申请日：1995-06-06

申请人： Charles R. Davis ,  Frank D. Egitto ,  Eugene R. Skarvinko

发明人： Charles R. Davis ,  Frank D. Egitto ,  Eugene R. Skarvinko

IPC分类号： H05K1/03 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498 ,  H01L23/538 ,  H05K1/00 ,  H05K3/00 ,  H05K3/46 ,  H01L21/268

CPC分类号： H05K3/0035 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L23/145 ,  H01L23/49894 ,  H01L23/5384 ,  H01L2924/0002 ,  H05K1/034 ,  H05K1/0373 ,  H05K2201/0195 ,  H05K2203/0207 ,  H05K3/4602 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4676 ,  Y10T428/24917 ,  Y10T428/25 ,  Y10T428/252 ,  Y10T428/3154 ,  Y10T428/31721

摘要： A multi-layer electronic circuit package including at least one electrically conductive plane, a first organic polymeric dielectric material having a first optical absorbency to an ablating wavelength of laser light, and a second organic polymeric dielectric material having a second optical absorbency to the ablating wavelength of laser light. The first and second optical absorbencies being different from each other. A first layer of one of the organic polymeric materials overlays at least one surface of the at least one electrically conductive plane and a second layer of a different organic polymeric material with a different optical absorbency to the material in the first layer overlays the first layer.

摘要翻译： 一种多层电子电路封装，包括至少一个导电平面，对激光的消融波长具有第一光学吸收性的第一有机聚合物电介质材料和具有对消融波长的第二光学吸收性的第二有机聚合物电介质材料 的激光。 第一和第二光吸收率彼此不同。 有机聚合材料之一的第一层覆盖至少一个导电平面的至少一个表面，并且具有与第一层中的材料不同的光学吸收性的不同有机聚合物材料的第二层覆盖在第一层上。

公开(公告)号：US5536579A

公开(公告)日：1996-07-16

申请号：US253084

申请日：1994-06-02

申请人： Charles R. Davis ,  Frank D. Egitto ,  Eugene R. Skarvinko

发明人： Charles R. Davis ,  Frank D. Egitto ,  Eugene R. Skarvinko

IPC分类号： H05K1/03 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498 ,  H01L23/538 ,  H05K1/00 ,  H05K3/00 ,  H05K3/46 ,  B32B9/00

CPC分类号： H05K3/0035 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L23/145 ,  H01L23/49894 ,  H01L23/5384 ,  H01L2924/0002 ,  H05K1/034 ,  H05K1/0373 ,  H05K2201/0195 ,  H05K2203/0207 ,  H05K3/4602 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4676 ,  Y10T428/24917 ,  Y10T428/25 ,  Y10T428/252 ,  Y10T428/3154 ,  Y10T428/31721

摘要： A multi-layer electronic circuit package including at least one electrically conductive plane, a first organic polymeric dielectric material having a first optical absorbency to an ablating wavelength of laser light, and a second organic polymeric dielectric material having a second optical absorbency to the ablating wavelength of laser light. The first material dielectric material absorbs wavelengths of light that are not the same as wavelengths of light that are absorbed by the second dielectric material. A first layer of the first or the second organic polymeric materials overlays at least one surface of the at least one electrically conductive plane and a second layer of the other of the first and second organic polymeric materials overlays the first layer.

摘要翻译： 一种多层电子电路封装，包括至少一个导电平面，对激光的消融波长具有第一光学吸收性的第一有机聚合物电介质材料和具有对消融波长的第二光学吸收性的第二有机聚合物电介质材料 的激光。 第一材料介电材料吸收与由第二介电材料吸收的光的波长不同的光的波长。 所述第一或第二有机聚合材料的第一层覆盖所述至少一个导电平面的至少一个表面，并且所述第一和第二有机聚合物材料中的另一个的第二层覆盖所述第一层。

公开(公告)号：US5460921A

公开(公告)日：1995-10-24

申请号：US118010

申请日：1993-09-08

申请人： Douglas A. Cywar ,  Charles R. Davis ,  Thomas P. Duffy ,  Frank D. Egitto ,  Paul J. Hart ,  Gerald W. Jones ,  Edward McLeskey

发明人： Douglas A. Cywar ,  Charles R. Davis ,  Thomas P. Duffy ,  Frank D. Egitto ,  Paul J. Hart ,  Gerald W. Jones ,  Edward McLeskey

IPC分类号： G03F7/00 ,  H05K1/09 ,  H05K3/00 ,  H05K3/10 ,  H05K3/12 ,  H05K3/40 ,  H05K3/46 ,  G03C5/00

CPC分类号： G03F7/00 ,  H05K3/0032 ,  H05K3/1258 ,  H05K3/4069 ,  H05K1/095 ,  H05K2201/015 ,  H05K2201/0209 ,  H05K2203/0191 ,  H05K2203/0568 ,  H05K2203/0769 ,  H05K2203/0783 ,  H05K2203/1383 ,  H05K3/0035 ,  H05K3/107 ,  H05K3/4664 ,  Y10S428/901 ,  Y10S430/146 ,  Y10T428/24917

摘要： The present invention provides a method of ablative photodecomposition and forming metal pattern which attains high resolution, is convenient, and employs non-halogenated solvents. The present invention is directed to a process for forming a metal pattern, preferably circuitization on an organic substrate, preferably on a circuit board or component thereof, which comprises coating the substrate with an ablatively-removable coating comprising a polymer resin preferably an acrylate polymer resin and preferably an ultraviolet absorber. A pattern is formed in the polymer coating corresponding to the desired metal pattern by irradiating at least a portion of the polymer coating with a sufficient amount of ultraviolet radiation to thereby ablatively remove the irradiated portion of the polymer coating. Next the patterned substrate is coated with a conductive metal paste to define the metal pattern, and the conductive metal paste is cured. The remaining polymer coating is removed by solvent stripping with non-halogenated solvents. The present invention further includes patterning electronic structures comprising multilayer circuitry using the above method. An excimer laser is used to form vias or through holes in the electronic structure while simultaneously patterning the polymer coating. This results in perfect alignment between the pattern formed in the polymer coating and the vias or through holes. High resolution circuitry is thus attainable when the electronic structure is subsequently metallized with a conductive metal paste.

摘要翻译： 本发明提供了一种烧蚀光分解和形成金属图案的方法，其获得高分辨率，方便并采用非卤化溶剂。 本发明涉及一种用于形成金属图案的方法，优选在有机基板上，优选在电路板或其组件上进行电路化，该方法包括用可剥离涂层涂覆基材，该涂层包含聚合物树脂，优选丙烯酸酯聚合物树脂 优选紫外线吸收剂。 通过用足够量的紫外线照射至少一部分聚合物涂层，形成对应于所需金属图案的聚合物涂层中的图案，从而消除聚合物涂层的照射部分。 接下来，用导电金属膏涂覆图案化衬底以限定金属图案，并且导电金属膏被固化。 通过用非卤化溶剂的溶剂汽提除去剩余的聚合物涂层。 本发明还包括使用上述方法图案化包括多层电路的电子结构。 准分子激光器用于在电子结构中形成通孔或通孔，同时构图聚合物涂层。 这导致在聚合物涂层中形成的图案与通孔或通孔之间完美对准。 因此，当电子结构随后用导电金属膏进行金属化时，可实现高分辨率电路。

公开(公告)号：US06650010B2

公开(公告)日：2003-11-18

申请号：US10078174

申请日：2002-02-15

申请人： Charles R. Davis ,  David L. Hawken ,  Dae Young Jung ,  William F. Landers ,  David L. Questad

发明人： Charles R. Davis ,  David L. Hawken ,  Dae Young Jung ,  William F. Landers ,  David L. Questad

IPC分类号： H01L2312

CPC分类号： H01L22/32 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/06131 ,  H01L2224/06155 ,  H01L2924/12044

摘要： A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.

摘要翻译： 在使用低k介电材料和铜基冶金的多层半导体器件中制造用于抑制分层和破裂的网状增强结构。 网状互连结构包括在每个布线层处由导线互连的导电焊盘，每个焊盘通过多个导电通孔在下一个布线电平下与其相邻的焊盘导电连接。 导电焊盘，线路和通孔在正常的BEOL布线级整合过程中制造。 加强结构提供垂直和水平加强件，并且可以在活动装置区域的周边或在易于分层和破裂的装置的开放区域内制造。

公开(公告)号：US5833666A

公开(公告)日：1998-11-10

申请号：US532236

申请日：1995-09-22

申请人： Charles R. Davis ,  David Schucart ,  Lev Melinyshyn

发明人： Charles R. Davis ,  David Schucart ,  Lev Melinyshyn

IPC分类号： A61M25/02

CPC分类号： A61M25/02 ,  A61M2025/024 ,  A61M2025/0273 ,  A61M2025/028 ,  Y10S128/26

摘要： An assembly for externally securing a catheter at or adjacent to an exit site on a body tissue which includes a resilient member and a detachably removable and adjustable clamp which allow for a gentle bend in the catheter so that kinking is prevented.

摘要翻译： 一种用于将导管外部固定在身体组织上的出口部位处或附近的组件，其包括弹性构件和可拆卸地可移动和可调节的夹子，其允许导管中的平缓弯曲，从而防止扭结。

公开(公告)号：US5280414A

公开(公告)日：1994-01-18

申请号：US536145

申请日：1990-06-11

申请人： Charles R. Davis ,  Richard Hsiao ,  James R. Loomis ,  Jae M. Park ,  Jonathan D. Reid

发明人： Charles R. Davis ,  Richard Hsiao ,  James R. Loomis ,  Jae M. Park ,  Jonathan D. Reid

IPC分类号： H01R43/02 ,  B23K35/00 ,  B23K35/30 ,  H01R4/02 ,  H05K3/28 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46 ,  H05K3/36 ,  B32B31/00 ,  H05K1/11

CPC分类号： B23K35/3013 ,  B23K35/001 ,  H01R4/02 ,  H05K3/4614 ,  H01L2924/0132 ,  H05K2201/0305 ,  H05K3/28 ,  H05K3/328 ,  H05K3/4038 ,  Y10S428/901 ,  Y10T156/1056 ,  Y10T29/49126

摘要： A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, multilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.

摘要翻译： 公开了一种同时层压电路化电介质层以形成多层高性能电路板并制造层间电连接的方法。 该方法选择将在一个低温下形成共晶体的两种元素，并且将固化形成合金，该合金将仅在任何后续层压所需的第二温度下再熔化。 使用瞬态液体粘合技术和足够的Au和Sn制成接头，以在低温下产生Au-Sn20wt％共晶。 一旦固化，形成的合金在随后的叠片中保持固体。 结果，制造复合多层高性能电路板，通过固体合金在选定的焊盘处电连接。

公开(公告)号：US06815346B2

公开(公告)日：2004-11-09

申请号：US10437208

申请日：2003-05-13

申请人： Charles R. Davis ,  David L. Hawken ,  Dae Young Jung ,  William F. Landers ,  David L. Questad

发明人： Charles R. Davis ,  David L. Hawken ,  Dae Young Jung ,  William F. Landers ,  David L. Questad

IPC分类号： H01L2144

CPC分类号： H01L22/32 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/06131 ,  H01L2224/06155 ,  H01L2924/12044

摘要： A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.

摘要翻译： 在使用低k介电材料和铜基冶金的多层半导体器件中制造用于抑制分层和破裂的网状增强结构。 网状互连结构包括在每个布线层处由导线互连的导电焊盘，每个焊盘通过多个导电通孔在下一个布线电平下与其相邻的焊盘导电连接。 导电焊盘，线路和通孔在正常的BEOL布线级整合过程中制造。 加强结构提供垂直和水平加强件，并且可以在活动装置区域的周边或在易于分层和破裂的装置的开放区域内制造。

公开(公告)号：US5878130A

公开(公告)日：1999-03-02

申请号：US67809

申请日：1998-04-28

申请人： G. Wayne Andrews ,  Steven H. Webber ,  James P. Kelly ,  Lawrence E. Johnson ,  Jerry A. Stern ,  Vincent J. Milano, Jr. ,  Charles R. Davis

发明人： G. Wayne Andrews ,  Steven H. Webber ,  James P. Kelly ,  Lawrence E. Johnson ,  Jerry A. Stern ,  Vincent J. Milano, Jr. ,  Charles R. Davis

IPC分类号： H04M3/22 ,  H04M3/36 ,  H04M3/493 ,  H04M3/51 ,  H04M3/523 ,  H04M7/12 ,  H04Q3/66 ,  H04Q3/72 ,  H04M7/06

CPC分类号： H04Q3/66 ,  H04M3/493 ,  H04M3/5191 ,  H04M3/5237 ,  H04M2242/22 ,  H04M3/22 ,  H04M3/36 ,  H04M3/42042 ,  H04M3/42059 ,  H04M3/42102 ,  H04M7/12 ,  H04Q2213/13034 ,  H04Q2213/1307 ,  H04Q2213/13072 ,  H04Q2213/13091 ,  H04Q2213/13103 ,  H04Q2213/13104 ,  H04Q2213/13141 ,  H04Q2213/13148 ,  H04Q2213/13167 ,  H04Q2213/13206 ,  H04Q2213/13209 ,  H04Q2213/1322 ,  H04Q2213/13288 ,  H04Q2213/13296 ,  H04Q2213/13349 ,  H04Q2213/13377 ,  H04Q2213/13389 ,  H04Q3/72

摘要： A communications system and method for automatically making telephone routing decisions with "global authority" based upon information gathered in real time from the entire communications system and global optimization criteria. The present invention permits unified central control and management for the entire system.

摘要翻译： 一种用于根据从整个通信系统实时收集的信息和全局优化标准自动地进行具有“全局授权”的电话路由决定的通信系统和方法。 本发明允许对整个系统进行统一的中央控制和管理。

公开(公告)号：US5384690A

公开(公告)日：1995-01-24

申请号：US97544

申请日：1993-07-27

申请人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

发明人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

IPC分类号： H01R4/26 ,  H01R4/58 ,  H01R12/61 ,  H01R13/66 ,  H05K1/00 ,  H05K1/03 ,  H05K1/14 ,  H05K3/00 ,  H05K3/32 ,  H05K3/46 ,  H01R23/68

CPC分类号： H05K3/4635 ,  H01R12/613 ,  H01R13/665 ,  H05K3/462 ,  H01R4/26 ,  H01R4/58 ,  H05K1/0373 ,  H05K1/0393 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10159 ,  H05K3/328 ,  H05K3/4623 ,  H05K3/4641 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49179 ,  Y10T428/24917

摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.

摘要翻译： 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。 各个子组件的层压是通过与要层压的区域中的子组件之间的全氟化碳聚合物化学相容（可粘合）化学相容的低熔点粘合剂，以及任选的与化学不相容的高熔点掩模 可粘合到）在不想层压的区域中的子组件之间的全氟化碳聚合物。 加热组件叠层以选择性地在要层压的区域中进行粘合和层压，同时避免在不想层压的区域中层压。

公开(公告)号：US5206074A

公开(公告)日：1993-04-27

申请号：US657795

申请日：1991-02-20

申请人： Charles R. Davis ,  Ashit A. Mehta ,  Konstantinos Papathomas ,  Lee P. Springer ,  William J. Summa ,  David W. Wang

发明人： Charles R. Davis ,  Ashit A. Mehta ,  Konstantinos Papathomas ,  Lee P. Springer ,  William J. Summa ,  David W. Wang

IPC分类号： C07D303/12 ,  C09J4/00 ,  H05K1/03

CPC分类号： C08G59/4014 ,  B32B15/08 ,  B32B15/20 ,  B32B27/06 ,  B32B27/34 ,  B32B7/12 ,  C08L63/00 ,  C08L79/08 ,  H05K1/034 ,  Y10S428/901 ,  Y10T428/24917

摘要： Disclosed is a polymeric product of diglycidyl bis phenol p-dialkyl benzene, and dicyanate diphenyl hexafluoro isopropane. Also disclosed is an organic polymeric dielectric composite of organic polymeric films, as polyimide films, dispersed in and reinforcing the organic polymeric adhesive reaction product of diglycidyl bis phenol p-dialkyl benzene, and dicyanate diphenyl hexafluoro isopropane. Further disclosed is an electronic circuit package that is adapted to receive at least one microelectronic circuit chip, with at least one layer having a substrate of an organic polymeric dielectric composite of organic polymeric films and the organic polymeric adhesive reaction product of diglycidyl bis phenol p-dialkyl benzene, and dicyanate diphenyl hexafluoro isopropane.

摘要翻译： 公开了二缩水甘油基双酚对二烷基苯和二氰基二苯基六氟异丙烷的聚合物。 还公开了分散在二缩水甘油基双酚对二烷基苯和二氰基二苯基六氟异丙苯的有机聚合物粘合反应产物中的有机聚合物膜作为聚酰亚胺膜的有机聚合物电介质复合材料。 还公开了一种电子电路封装，其适于接收至少一个微电子电路芯片，其中至少一层具有有机聚合物膜的有机聚合物电介质复合材料的基底和二缩水甘油基双酚对苯二甲酸的有机聚合物粘合反应产物， 二苯基苯和二氰基二苯基六氟异丙苯。