公开(公告)号：US20070045784A1

公开(公告)日：2007-03-01

申请号：US11212440

申请日：2005-08-25

申请人： David Corisis ,  Chin Chong ,  Lee Kuan

发明人： David Corisis ,  Chin Chong ,  Lee Kuan

IPC分类号： H01L23/495

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15183 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A lead frame-based semiconductor device package including at least one land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. The terminal pads of the interposer substrate may be electrically connected to both a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. The assembly is overmolded with an encapsulant, leaving the opposing side of the interposer substrate free of encapsulant. Lead fingers of a lead frame superimposed on the opposing side of the interposer substrate are bonded directly to the land grid array lands. Two land grid array packages as previously described may be superimposed on opposing sides of lead fingers of a lead frame disposed therebetween and electrically connected thereto. Methods of fabrication are also disclosed.

摘要翻译： 一种引线框架半导体器件封装，其包括至少一个焊盘阵列封装。 至少一个半导体管芯安装到插入器衬底上，其中半导体管芯的接合焊盘连接到与至少一个半导体管芯在内插器衬底的同一侧上的端子焊盘。 插入器基板的端子焊盘可以电连接到焊盘的外围阵列图案和焊盘的中心的二维阵列图案，两个阵列图案位于中介层衬底的与至少一个半导体的相对侧上 死。 组件用密封剂包覆成型，留下中介层基板的相对侧不含密封剂。 叠置在插入器基板的相对侧上的引线框架的引线指向栅格阵列阵列直接接合。 如前所述的两个焊盘阵列封装可以叠置在设置在它们之间并与之电连接的引线框架的引线指的相对侧上。 还公开了制造方法。

公开(公告)号：US20070194431A1

公开(公告)日：2007-08-23

申请号：US11359863

申请日：2006-02-22

申请人： David Corisis ,  Lee Kuan ,  Chin Chong

发明人： David Corisis ,  Lee Kuan ,  Chin Chong

IPC分类号： H01L23/04 ,  H05K1/00

CPC分类号： H05K1/115 ,  G01R31/026 ,  G06F1/16 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0221 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0296 ,  H05K1/18 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09809 ,  Y10T29/49165 ,  H01L2924/00

摘要： Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

摘要翻译： 电子器件包括具有在衬底中或衬底上延伸的第一和第二对导电迹线的衬底。 第一导电互连构件延伸穿过衬底中的孔并且与第一和第二对中的每一个的第一迹线电连通，而第二导电互连构件延伸穿过孔并与第一导电互连构件中的每一个的第二迹线电连通 和第二对。 第一和第二互连构件彼此间隔开距离，该距离基本上等于分隔每对导电迹线的距离。 电子设备组件包括被配置为通过导电结构将差分信号传输到接收设备的发送设备。 导电结构包括第一和第二对导电迹线，其中第一和第二互连构件之间提供电连通。

公开(公告)号：US20070045818A1

公开(公告)日：2007-03-01

申请号：US11212215

申请日：2005-08-25

申请人： Lee Kuan ,  David Corisis ,  Chin Chong

发明人： Lee Kuan ,  David Corisis ,  Chin Chong

IPC分类号： H01L23/12 ,  H01L21/58

CPC分类号： H01L24/92 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/49531 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92127 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. Terminal pads of the interposer substrate may be electrically connected to either or both of a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. Additional components, active, passive or both, may be connected to pads of the two-dimensional array to provide a system-in-a-package. Lead fingers of a lead frame may be superimposed on the opposing side of the interposer substrate, bonded directly to the land grid array land and wire bonded to pads as desired for repair or to ease routing problems on the interposer. The land grid array package may be mounted to a carrier substrate, and the lands wire bonded to conductive pads on the carrier substrate. Methods of fabrication are also disclosed.

摘要翻译： 半导体器件封装包括焊盘栅格阵列封装。 至少一个半导体管芯安装到插入器衬底上，其中半导体管芯的接合焊盘连接到与至少一个半导体管芯在内插器衬底的同一侧上的端子焊盘。 插入器基板的端子焊盘可以电连接到焊盘的外围阵列图案中的一个或两个以及中心的二维阵列阵列图案，两个阵列图案位于至少从中间层基板的相对侧起至少 一个半导体芯片。 可以将主动，被动或两者的附加组件连接到二维阵列的焊盘以提供系统级封装。 引线框架的引脚可以叠置在插入器基板的相对侧上，直接接合到焊盘栅格阵列焊盘，并且焊接到焊盘上，以便修理或者简化插入器上的布线问题。 焊盘阵列封装可以安装到载体衬底上，焊盘引线键合到载体衬底上的导电焊盘上。 还公开了制造方法。

公开(公告)号：US20070249100A1

公开(公告)日：2007-10-25

申请号：US11677291

申请日：2007-02-21

申请人： David Corisis ,  Lee Kuan ,  Chong Hui

发明人： David Corisis ,  Lee Kuan ,  Chong Hui

IPC分类号： H01L21/00

CPC分类号： H01L23/3107 ,  H01L21/568 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/207

摘要： Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.

摘要翻译： 公开了用于集成电路器件的无载体芯片封装，以及制造相同的各种方法。 在一个说明性实施例中，该器件包括集成电路芯片，该集成电路芯片包括限定平面的暴露的背面，与该集成电路芯片导电耦合的多个引线键合，多个引线键合中的每一个导电耦合到导电暴露 导电暴露部分的一部分位于由背侧表面限定的平面中，以及邻近集成电路芯片定位的密封材料和多个引线键合。

公开(公告)号：US20070045862A1

公开(公告)日：2007-03-01

申请号：US11217749

申请日：2005-09-01

申请人： David Corisis ,  Chong Hui ,  Lee Kuan

发明人： David Corisis ,  Chong Hui ,  Lee Kuan

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/561 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Stacked microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such microelectronic device can include a support member and a first known good microelectronic die attached to the support member. The first die includes an active side, a back side opposite the active side, a first terminal at the active side, and integrated circuitry electrically coupled to the first terminal. The first die also includes a first redistribution structure at the active side of the first die. The microelectronic device can also include a second known good microelectronic die attached to the first die in a stacked configuration such that a back side of the second die is facing the support member and an active side of the second die faces away from the support member. The second die includes a second redistribution structure at the active side of the second die. The device can further include a casing covering the first die, the second die, and at least a portion of the support member.

摘要翻译： 本文公开了堆叠的微电子器件和用于制造微电子器件的方法。 一个这样的微电子器件的实施例可以包括支撑构件和附接到支撑构件的第一已知的良好微电子管芯。 第一管芯包括有源侧，与有源侧相对的背面，在有源侧上的第一端子，以及电耦合到第一端子的集成电路。 第一管芯还包括在第一管芯的主动侧的第一再分配结构。 微电子器件还可以包括以堆叠构造附接到第一管芯的第二已知的良好微电子管芯，使得第二管芯的背面面向支撑构件，并且第二管芯的有效侧面远离支撑构件。 第二管芯包括在第二管芯的有源侧的第二再分布结构。 该装置还可以包括覆盖第一模具，第二模具和支撑构件的至少一部分的壳体。

公开(公告)号：US20070216033A1

公开(公告)日：2007-09-20

申请号：US11384734

申请日：2006-03-20

申请人： David Corisis ,  Lee Kuan ,  Chong Hui

发明人： David Corisis ,  Lee Kuan ,  Chong Hui

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L23/3107 ,  H01L21/568 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/207

摘要： Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.

摘要翻译： 公开了用于集成电路器件的无载体芯片封装，以及制造相同的各种方法。 在一个说明性实施例中，该器件包括集成电路芯片，该集成电路芯片包括限定平面的暴露的背面，与该集成电路芯片导电耦合的多个引线键合，多个引线键合中的每一个导电耦合到导电暴露 导电暴露部分的一部分位于由背侧表面限定的平面中，以及邻近集成电路芯片定位的密封材料和多个引线键合。

公开(公告)号：US20050087847A1

公开(公告)日：2005-04-28

申请号：US10998380

申请日：2004-11-29

申请人： Lee Kuan ,  Chong Hui ,  Lee Lai

发明人： Lee Kuan ,  Chong Hui ,  Lee Lai

IPC分类号： H01L23/31 ,  H01L23/495

CPC分类号： H01L24/91 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49537 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a semiconductor die having a circuit side and a back side, a multi layered leadframe attached to the die, a dense array of terminal contacts in electrical communication with the die, and a plastic body encapsulating the die and the leadframe. The leadframe includes circuit side leads attached to the circuit side of the die, and back side leads located proximate to the back side of the die. Both the circuit side leads and the back side leads are wire bonded to bond pads on the die. In addition, the back side leads provide electrical paths between the bond pads and selected terminal contacts that would otherwise be inaccessible due to line/space design rules. A method for fabricating the package includes the steps of: attaching the die to the circuit side leads, attaching the back side leads to the circuit side leads, wire bonding the die to the leads, encapsulating the die, and then forming the terminal contacts.

摘要翻译： 半导体封装包括具有电路侧和背面的半导体管芯，附接到管芯的多层引线框架，与管芯电连通的端子触头的密集阵列，以及封装管芯和引线框架的塑料体。 引线框架包括附接到模具的电路侧的电路侧引线以及靠近模具背面的背面引线。 电路侧引线和后侧引线都与引线接合在芯片上的接合焊盘上。 另外，背面引线提供接合焊盘和所选择的端子触点之间的电路径，否则由于线/空间设计规则将不可访问。 一种制造封装的方法，包括以下步骤：将裸片连接到电路侧引线，将背面引线连接到电路侧引线，将管芯引线接合到引线，封装管芯，然后形成端子触头。

公开(公告)号：US20050023651A1

公开(公告)日：2005-02-03

申请号：US10633434

申请日：2003-08-01

申请人： Dalson Kim ,  Jeffrey Fook ,  Lee Kuan

发明人： Dalson Kim ,  Jeffrey Fook ,  Lee Kuan

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L21/50 ,  H01L21/44 ,  H01L21/48 ,  H01L23/02

CPC分类号： H01L23/495 ,  B33Y70/00 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/4952 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/86 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012

摘要： A semiconductor component includes a chip on board leadframe, a semiconductor die back bonded and wire bonded to the leadframe, an encapsulant on the die and an area array of terminal contacts on the leadframe. The leadframe includes leadfingers, interconnect bonding sites for wire bonding the die, terminal bonding sites for the terminal contacts, and bus bars which electrically connect selected leadfingers to one another. The interconnect bonding sites are located on the leadframe relative to the bus bars such that shorting to the bus bars by wire interconnects is eliminated. A method for fabricating the component includes the steps of attaching the die to the leadframe, bonding the wire interconnects to the die and to the interconnect bonding sites, forming the encapsulant, and then forming the terminal contacts on the terminal bonding sites.

摘要翻译： 半导体部件包括：芯片上的引线框架，半导体管芯接合和引线接合引线框架，芯片上的密封剂和引线框架上的端子触点的区域阵列。 引线框架包括引线端子，用于引线接合管芯的互连结合部位，用于端子触头的端子接合部位和将所选择的引线彼此电连接的母线。 互连结合位置相对于母线位于引线框架上，从而消除了通过线互连对母线的短路。 一种用于制造该部件的方法包括以下步骤：将裸片连接到引线框架，将导线互连件连接到管芯和互连接合部位，形成密封剂，然后在端子接合位置形成端子触点。

公开(公告)号：US20070194415A1

公开(公告)日：2007-08-23

申请号：US11359985

申请日：2006-02-22

申请人： Eric Seng ,  Lee Kuan

发明人： Eric Seng ,  Lee Kuan

IPC分类号： H01L21/44 ,  H01L23/02

CPC分类号： H01L25/0657 ,  H01L21/44 ,  H01L24/48 ,  H01L24/49 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48221 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06575 ,  H01L2225/06579 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： Semiconductor device assemblies include at least first and second semiconductor dice disposed in a face-to-face configuration. At least some of a plurality of conductive structures are electrically and structurally coupled to a bond pad of the first semiconductor die and a bond pad of the second semiconductor die. A first end of each of a plurality of laterally extending conductive elements may be structurally and electrically coupled to a conductive terminal of a substrate, and a second end of each laterally extending conductive element is structurally and electrically coupled to at least one of a bond pad of the first semiconductor die, a bond pad of the second semiconductor die, and a conductive structure. Methods include the fabrication of such assemblies. Electronic systems include at least one electronic signal processing device, at least one input or output device, and at least one memory device including such a semiconductor device assembly.

摘要翻译： 半导体器件组件包括以面对面配置布置的至少第一和第二半导体晶片。 多个导电结构中的至少一些电学上和结构上耦合到第一半导体管芯的接合焊盘和第二半导体管芯的接合焊盘。 多个横向延伸的导电元件中的每一个的第一端可以在结构上和电耦合到衬底的导电端子，并且每个横向延伸的导电元件的第二端在结构上和电耦合到至少一个接合焊盘 的第一半导体管芯，第二半导体管芯的接合焊盘以及导电结构。 方法包括制造这种组件。 电子系统包括至少一个电子信号处理装置，至少一个输入或输出装置以及包括这种半导体装置组件的至少一个存储装置。

公开(公告)号：US20050029552A1

公开(公告)日：2005-02-10

申请号：US10931844

申请日：2004-08-31

申请人： Lee Kuan ,  Lee Chai

发明人： Lee Kuan ,  Lee Chai

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H01L27/148

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/10568 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2201/2036 ,  Y02P70/613 ,  Y10S438/926 ,  Y10S438/928 ,  Y10T428/24 ,  Y10T428/24802 ,  Y10T428/24917 ,  H01L2924/00

摘要： A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to stiffen the substrate adapted to mount one or more dice, one or more dice mounted on the substrate and a molding compound to attach the substrate to the package substrate.

摘要翻译： 一种包括封装基板的封装，包括基板的模具基板组件，所述基板包括多个层，所述基板包括具有网状物的层，所述层具有适于安装一个或多个骰子的基板以加固所述基板，一个或多个骰子安装在所述基板上， 以将衬底附接到封装衬底。