公开(公告)号：US07250330B2

公开(公告)日：2007-07-31

申请号：US10282975

申请日：2002-10-29

申请人： David L. Thomas ,  Charles G. Woychik

发明人： David L. Thomas ,  Charles G. Woychik

IPC分类号： H01L21/00 ,  H01L21/30

CPC分类号： H01L23/49816 ,  H01L23/49894 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2224/0401

摘要： A method of making an electronic package is described, wherein a substrate is provided with a pattern of conductive pads and a portion of solder positioned on selected ones of the pattern of copper pads. The solder is then reflowed to form partial hemispherically shaped caps on the selected copper pads. The partial hemispherically shaped caps are then coated with a solder flux. A thin semiconductor chip with a pattern of conductive elements, corresponding to partial hemispherically shaped capped pads, is then positioned on the substrate so that the conductive elements of the thin semiconductor chip substantially line up with the partial hemispherically shaped capped pads of the substrate. The solder is then heated to reflow temperature and an electrical couple is formed between the thin semiconductor chip and the substrate. Since all the solder necessary to make the electrical couple is positioned on the substrate, it is possible to use a thin semiconductor chip in the electronic package avoiding the problem presented by the handling and processing steps associated with securing a bumped wafer substrate during the thinning process and in subsequent processes of making the thinned semiconductor chip from the bumped wafer, for example, the dicing step.

摘要翻译： 描述了一种制造电子封装件的方法，其中衬底设置有导电焊盘的图案和位于铜焊盘上的所选图案上的焊料的一部分。 然后将焊料回流以在选定的铜焊盘上形成部分半球形帽。 然后用焊剂涂覆部分半球形盖。 然后将具有对应于部分半球形封盖焊盘的导电元件图案的薄半导体芯片定位在基板上，使得薄半导体芯片的导电元件基本上与衬底的部分半球形封盖焊盘对齐。 然后将焊料加热回流温度，并在薄的半导体芯片和衬底之间形成电耦合。 由于制造电耦合所需的所有焊料都位于基板上，所以可以在电子封装中使用薄的半导体芯片，避免了在薄化处理期间固定凸起的晶片衬底的处理和处理步骤所带来的问题 以及在从凸起的晶片制造变薄的半导体芯片的后续工艺中，例如，切割步骤。

公开(公告)号：US20130001757A1

公开(公告)日：2013-01-03

申请号：US13173883

申请日：2011-06-30

申请人： Chok Chia ,  Qwai Low ,  Kishor Desai ,  Charles G. Woychik

发明人： Chok Chia ,  Qwai Low ,  Kishor Desai ,  Charles G. Woychik

IPC分类号： H01L23/495 ,  H01R43/16 ,  H01L21/50 ,  H01L23/34 ,  H01L21/60

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/11332 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2224/1339 ,  H01L2224/13401 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2224/8184 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/07811 ,  Y10T29/49204 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/00

摘要： A microelectronic unit can include a lead frame and a device chip. The lead frame can have a plurality of monolithic lead fingers extending in a plane of the lead frame. Each lead finger can have a fan-out portion and a chip connection portion extending in the lead frame plane. The fan-out portions can have first and second opposed surfaces and a first thickness in a first direction between the opposed surfaces. The chip connection portions can have a second thickness smaller than the first thickness. The chip connection portions can define a recess below the first surface. The device chip can have a plurality of at least one of passive devices or active devices. The device chip can have contacts thereon facing the chip connection portions and electrically coupled thereto. At least a portion of a thickness of the device chip can extend within the recess.

摘要翻译： 微电子单元可以包括引线框架和器件芯片。 引线框架可以具有在引线框架的平面中延伸的多个单片引线指。 每个引线指可以具有在引线框架平面中延伸的扇出部分和芯片连接部分。 扇出部分可以在相对的表面之间具有第一和第二相对表面以及在第一方向上的第一厚度。 芯片连接部分可以具有小于第一厚度的第二厚度。 芯片连接部分可以限定第一表面下方的凹陷。 器件芯片可以具有多个无源器件或有源器件中的至少一个。 器件芯片可以具有面向芯片连接部分并且与其电耦合的触点。 装置芯片的厚度的至少一部分可以在凹部内延伸。

公开(公告)号：US20120314384A1

公开(公告)日：2012-12-13

申请号：US13156609

申请日：2011-06-09

申请人： Charles G. Woychik ,  Kishor Desai ,  Ilyas Mohammed ,  Terrence Caskey

发明人： Charles G. Woychik ,  Kishor Desai ,  Ilyas Mohammed ,  Terrence Caskey

IPC分类号： H05K5/00 ,  H01L21/768 ,  H05K7/00 ,  H05K1/09 ,  H05K1/11 ,  H05K1/00

CPC分类号： H05K3/0094 ,  B23K1/0016 ,  B23K35/24 ,  B23K35/36 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49883 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/09701 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.

摘要翻译： 部件可以包括具有第一表面和远离其的第二表面的基板，沿着第一和第二表面之间的方向延伸的开口以及在开口内延伸的导电通孔。 基底可以具有小于10ppm /℃的CTE。导电通孔可以包括多个基础颗粒，每个基底颗粒包括基本上被不同于第一金属的第二金属层覆盖的第一金属的第一区域。 基础颗粒可以冶金学连接在一起，并且颗粒的第二金属层可以至少部分地扩散到第一区域中。 导电通孔可以包括散布在接合的基础颗粒之间的空隙。 空隙可以占据导电通孔体积的10％或更多。

公开(公告)号：US20100133683A1

公开(公告)日：2010-06-03

申请号：US12326202

申请日：2008-12-02

申请人： Raymond Albert Fillion ,  Kevin M. Durocher ,  Elizabeth A. Burke ,  Thomas Bert Gorczyca ,  Charles G. Woychik

发明人： Raymond Albert Fillion ,  Kevin M. Durocher ,  Elizabeth A. Burke ,  Thomas Bert Gorczyca ,  Charles G. Woychik

IPC分类号： H01L23/34 ,  H01L23/00 ,  H01L21/02

CPC分类号： H01L23/49822 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/564 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： An apparatus and method, the apparatus includes a substrate configured to support a plurality of dielectric layers, a device coupling area positioned in the substrate, and a plurality of gas exit apertures formed through the substrate. The plurality of gas exit apertures is configured to provide venting of at least one of moisture and outgassed material and the device coupling area is configured to receive an electronic device coupleable to the plurality of dielectric layers.

摘要翻译： 一种装置和方法，所述装置包括被配置为支撑多个电介质层的基板，位于所述基板中的装置耦合区域以及穿过所述基板形成的多个气体出口孔。 多个气体出口孔被配置为提供湿气和脱气材料中的至少一种的排气，并且装置联接区域被配置为接收可耦合到多个电介质层的电子装置。

公开(公告)号：US06293455B1

公开(公告)日：2001-09-25

申请号：US09649318

申请日：2000-08-28

申请人： David V. Caletka ,  Kevin Knadle ,  Charles G. Woychik

发明人： David V. Caletka ,  Kevin Knadle ,  Charles G. Woychik

IPC分类号： B23K3112

CPC分类号： B23K3/08 ,  H05K1/0201 ,  H05K3/3494 ,  H05K2201/10151 ,  H05K2203/081 ,  H05K2203/1121

摘要： A method and an arrangement for measuring the cooling rate and thermal gradient between the top and bottom surfaces of a printed circuit board. Moreover, it is intended to facilitate control over the temperature gradient which is encountered between the top and bottom of the PCB so as to prevent warpage thereof during the formation of solder joints in a reflow solder oven.

摘要翻译： 一种用于测量印刷电路板的顶表面和底表面之间的冷却速率和热梯度的方法和装置。 此外，旨在便于控制PCB顶部和底部之间遇到的温度梯度，以防止在回流焊料炉中形成焊点期间的翘曲。

公开(公告)号：US5201451A

公开(公告)日：1993-04-13

申请号：US727047

申请日：1991-07-09

申请人： Kishor V. Desai ,  Nelson P. Franchak ,  Robert H. Katyl ,  Harold Kohn ,  Endwell ,  Tamar A. Sholtes ,  Vilakkudi G. Veeraraghavan ,  Charles G. Woychik

发明人： Kishor V. Desai ,  Nelson P. Franchak ,  Robert H. Katyl ,  Harold Kohn ,  Endwell ,  Tamar A. Sholtes ,  Vilakkudi G. Veeraraghavan ,  Charles G. Woychik

IPC分类号： H01L21/98 ,  H01L23/498 ,  H01L23/538 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC分类号： H01L25/50 ,  H01L23/4985 ,  H01L23/5385 ,  H05K3/3478 ,  H05K3/363 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H05K1/141 ,  H05K2201/0215 ,  H05K2201/049 ,  H05K2201/10234 ,  H05K2201/10477 ,  H05K2201/10681 ,  H05K2201/10734 ,  H05K2201/10984 ,  H05K2203/0165 ,  H05K2203/0278 ,  H05K2203/041 ,  H05K2203/0557

摘要： Method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier on a second level electronic package. The resulting electronic packaging structure includes electrically conductive spacers, such as solder balls or solder coated copper balls, which electrically interconnect outer lead bonding pads on the flexible film semiconductor chip carrier and corresponding bonding pads on the second level electronic package, and which physically support the flexible film of the semiconductor chip carrier substantially in a plane above the surface of the second level electronic package. This electronic packaging structure is made using a special assembly fixture comprising a base plate, a pressure insert with a resilient member, and a top plate. The flexible film semiconductor chip carrier with the spacers attached thereto is placed over the resilient member of the pressure insert which is clamped together with the second level electronic package between the top and base plates. Then, this assembly is heated to reflow the solder of the spacers, and the assembly fixture is disassembled,; leaving the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired.

摘要翻译： 公开了用于将柔性膜半导体芯片载体安装在第二级电子封装上的方法和装置。 所得到的电子封装结构包括导电间隔物，例如焊球或焊料涂覆的铜球，其将柔性膜半导体芯片载体上的外引线接合焊盘和第二级电子封装上的对应焊盘电互连，并且物理地支撑 所述半导体芯片载体的柔性膜基本上在所述第二级电子封装的表面上方的平面中。 该电子包装结构使用特殊的组装夹具制成，该组装夹具包括基板，具有弹性构件的压力插入件和顶板。 具有附接到其上的间隔物的柔性膜半导体芯片载体被放置在压力插入件的弹性构件上，该压力插入件与顶层和底板之间的第二级电子封装夹紧在一起。 然后，将该组件加热以回流间隔件的焊料，并拆卸组装夹具。 留下安装在第二级电子封装上的柔性膜半导体芯片载体，其中载体的柔性膜具有所需的平面几何形状。

公开(公告)号：US5159535A

公开(公告)日：1992-10-27

申请号：US365326

申请日：1989-06-13

申请人： Kishor V. Desai ,  Nelson P. Franchak ,  Robert H. Katyl ,  Harold Kohn ,  Tamar A. Sholtes ,  Vilakkudi G. Veeraraghavan ,  Charles G. Woychik

发明人： Kishor V. Desai ,  Nelson P. Franchak ,  Robert H. Katyl ,  Harold Kohn ,  Tamar A. Sholtes ,  Vilakkudi G. Veeraraghavan ,  Charles G. Woychik

IPC分类号： H01L21/98 ,  H01L23/498 ,  H01L23/538 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC分类号： H01L25/50 ,  H01L23/4985 ,  H01L23/5385 ,  H05K3/3478 ,  H05K3/363 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15321 ,  H05K1/141 ,  H05K2201/0215 ,  H05K2201/049 ,  H05K2201/10234 ,  H05K2201/10477 ,  H05K2201/10681 ,  H05K2201/10734 ,  H05K2201/10984 ,  H05K2203/0165 ,  H05K2203/0278 ,  H05K2203/041 ,  H05K2203/0557

摘要： Method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier on a second level electronic package. The resulting electronic packaging structure includes electrically conductive spacers, such as solder balls or solder coated copper balls, which electrically interconnect outer lead bonding pads on the flexible film semiconductor chip carrier and corresponding bonding pads on the second level electronic package, and which physically support the flexible film of the semiconductor chip carrier substantially in a plane above the surface of the second level electronic package. This electronic packaging structure is made using a special assembly fixture comprising a base plate, a pressure insert with a resilient member, and a top plate. The flexible film semiconductor chip carrier with the spacers attached thereto is placed over the resilient member of the pressure insert which is clamped together with the second level electronic package between the top and base plates. Then, this assembly is heated to reflow the solder of the spacers, and the assembly fixture is disassembled, leaving the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired. The spacers may be attached to the flexible film semiconductor chip carrier using a special template having a pattern of openings corresponding to the pattern of outer lead bonding pads on the flexible film semiconductor chip carrier.

摘要翻译： 公开了用于将柔性膜半导体芯片载体安装在第二级电子封装上的方法和装置。 所得到的电子封装结构包括导电间隔物，例如焊球或焊料涂覆的铜球，其将柔性膜半导体芯片载体上的外引线接合焊盘和第二级电子封装上的对应焊盘电互连，并且物理地支撑 所述半导体芯片载体的柔性膜基本上在所述第二级电子封装的表面上方的平面中。 该电子包装结构使用特殊的组装夹具制成，该组装夹具包括基板，具有弹性构件的压力插入件和顶板。 具有附接到其上的间隔物的柔性膜半导体芯片载体被放置在压力插入件的弹性构件上，该压力插入件与顶层和底板之间的第二级电子封装夹紧在一起。 然后，将该组件加热以回流间隔件的焊料，并且组装夹具被拆卸，使得柔性膜半导体芯片载体安装在第二层电子封装上，其中载体的柔性膜根据需要具有平面几何形状。 可以使用具有对应于柔性膜半导体芯片载体上的外引线接合焊盘的图案的开口图案的特殊模板将间隔件附接到柔性膜半导体芯片载体。

公开(公告)号：US5075965A

公开(公告)日：1991-12-31

申请号：US608766

申请日：1990-11-05

申请人： Charles F. Carey ,  Kenneth M. Fallon ,  Rochelle Ginsburg ,  Charles G. Woychik

发明人： Charles F. Carey ,  Kenneth M. Fallon ,  Rochelle Ginsburg ,  Charles G. Woychik

IPC分类号： B23K1/00 ,  H01L21/60 ,  H05K3/34

CPC分类号： H01L24/81 ,  B23K1/0016 ,  H05K3/3436 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K2201/10992 ,  H05K2203/0415 ,  H05K3/3431 ,  H05K3/3457 ,  Y02P70/613 ,  Y10T29/49144

摘要： A controlled collapse chip connect method of joining an IC chip to a microelectronic circuit card. According to the method an inhomogeneous, anisotropic column of solder is deposited from a Pb/Sn alloy onto solder wettable I/O terminals of the I/C chip, without subsequent homogenizing reflow. The solder core has a Pb rich core and an Sn rich cap. The matching footprint of the solder wettable I/O terminals on the microelectronic circuit card is substantially free of deposited solder and presents a protected Cu surface to the solder columns, or, at most a surface of Cu and anti-oxidant. The chip is aligned with the corresponding footprints on the microelectronic circuit card, and the solder is reflowed to bond the chip to the microelectronic circuit card.

公开(公告)号：US08723049B2

公开(公告)日：2014-05-13

申请号：US13156609

申请日：2011-06-09

申请人： Charles G. Woychik ,  Kishor Desai ,  Ilyas Mohammed ,  Terrence Caskey

发明人： Charles G. Woychik ,  Kishor Desai ,  Ilyas Mohammed ,  Terrence Caskey

IPC分类号： H05K1/11

CPC分类号： H05K3/0094 ,  B23K1/0016 ,  B23K35/24 ,  B23K35/36 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49883 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/09701 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.

摘要翻译： 部件可以包括具有第一表面和远离其的第二表面的基板，沿着第一和第二表面之间的方向延伸的开口以及在开口内延伸的导电通孔。 基底可以具有小于10ppm /℃的CTE。导电通孔可以包括多个基础颗粒，每个基底颗粒包括基本上被不同于第一金属的第二金属层覆盖的第一金属的第一区域。 基础颗粒可以冶金学连接在一起，并且颗粒的第二金属层可以至少部分地扩散到第一区域中。 导电通孔可以包括散布在接合的基础颗粒之间的空隙。 空隙可以占据导电通孔体积的10％或更多。

公开(公告)号：US08525309B2

公开(公告)日：2013-09-03

申请号：US13173883

申请日：2011-06-30

申请人： Chok Chia ,  Qwai Low ,  Kishor Desai ,  Charles G. Woychik

发明人： Chok Chia ,  Qwai Low ,  Kishor Desai ,  Charles G. Woychik

IPC分类号： H01L23/495 ,  H01L21/50 ,  H01L23/34 ,  H01L21/60 ,  H01R43/16

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/11332 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2224/1339 ,  H01L2224/13401 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2224/8184 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/07811 ,  Y10T29/49204 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/00

摘要： A microelectronic unit can include a lead frame and a device chip. The lead frame can have a plurality of monolithic lead fingers extending in a plane of the lead frame. Each lead finger can have a fan-out portion and a chip connection portion extending in the lead frame plane. The fan-out portions can have first and second opposed surfaces and a first thickness in a first direction between the opposed surfaces. The chip connection portions can have a second thickness smaller than the first thickness. The chip connection portions can define a recess below the first surface. The device chip can have a plurality of at least one of passive devices or active devices. The device chip can have contacts thereon facing the chip connection portions and electrically coupled thereto. At least a portion of a thickness of the device chip can extend within the recess.

摘要翻译： 微电子单元可以包括引线框架和器件芯片。 引线框架可以具有在引线框架的平面中延伸的多个单片引线指。 每个引线指可以具有在引线框架平面中延伸的扇出部分和芯片连接部分。 扇出部分可以在相对的表面之间具有第一和第二相对表面以及在第一方向上的第一厚度。 芯片连接部分可以具有小于第一厚度的第二厚度。 芯片连接部分可以限定第一表面下方的凹陷。 器件芯片可以具有多个无源器件或有源器件中的至少一个。 器件芯片可以具有面向芯片连接部分并且与其电耦合的触点。 装置芯片的厚度的至少一部分可以在凹部内延伸。