公开(公告)号：US5701085A

公开(公告)日：1997-12-23

申请号：US498791

申请日：1995-07-05

申请人： Deviprasad Malladi ,  Lee Frederick Hanson ,  Jean Kahahane

发明人： Deviprasad Malladi ,  Lee Frederick Hanson ,  Jean Kahahane

IPC分类号： G01R1/04 ,  G01R31/28 ,  G01R1/07

CPC分类号： G01R31/2886 ,  G01R1/0483 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73253 ,  H01L2924/1515 ,  H01L2924/15311

摘要： An apparatus for use in testing wire bond or flip chip connected integrated circuits includes a housing with a top side, a bottom side, and a perimeter region defining a housing central aperture. The housing further includes flip chip pads to accommodate flip chip solder connections to a flip chip integrated circuit during a first test period and wire bond pads to accommodate wire bond connections to a wire bond integrated circuit during a second test period. There are connector pins on the bottom side of the housing for connection with a printed circuit board. The printed circuit board includes an access aperture which is aligned with the housing central aperture. This configuration allows a test probe to access a flip chip integrated circuit positioned within the housing. It also allows a heat sink to be used when the housing incorporates a wire bonded integrated circuit.

摘要翻译： 用于测试引线接合或倒装芯片连接的集成电路的装置包括具有顶侧，底侧和限定壳体中心孔的周边区域的壳体。 壳体还包括倒装芯片焊盘，以在第一测试周期期间适应倒装芯片焊接连接到倒装芯片集成电路，并且引线接合焊盘以在第二测试周期期间适应引线键合连接到引线接合集成电路。 在外壳底部有连接器针脚，用于与印刷电路板连接。 印刷电路板包括与壳体中心孔对准的进入孔。 该配置允许测试探针访问位于壳体内的倒装芯片集成电路。 它还允许当外壳包含导线接合集成电路时使用散热器。

公开(公告)号：US07939364B2

公开(公告)日：2011-05-10

申请号：US12121337

申请日：2008-05-15

申请人： Vadim Gektin ,  Deviprasad Malladi

发明人： Vadim Gektin ,  Deviprasad Malladi

IPC分类号： H01L21/00

CPC分类号： H01L23/42 ,  H01L23/4275 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/16195

摘要： A multi-surface compliant heat removal process includes: identifying one or more components to share a heat rejecting device, applying non-adhesive film to the one or more components, identifying a primary component of the one or more components, and applying phase change material on each of the one or more components other than the primary component. The phase change material is placed on top of the non-adhesive film. The process further includes placing the heat rejecting device on the corresponding one or more components and removing the heat rejecting device from the corresponding one or more components. The phase change material and the non-adhesive film remain with the heat rejecting device. The process also includes reflowing the phase change material on the heat rejecting device, removing the non-adhesive film from the heat rejecting device, placing a heatsink-attach thermal interface material on the one or more components, and placing the heat rejecting device on the corresponding one or more components.

摘要翻译： 多表面兼容的热去除方法包括：识别一个或多个部件以共享热拒绝装置，将非粘合膜施加到所述一个或多个部件，识别所述一个或多个部件的主要部件，以及施加相变材料 在除主要部件之外的一个或多个部件的每一个上。 相变材料放置在非粘合膜的顶部。 该方法还包括将散热装置放置在相应的一个或多个部件上，并从相应的一个或多个部件移除散热装置。 相变材料和非粘合膜保留在散热装置上。 该方法还包括在排热装置上回流相变材料，从热排出装置中去除非粘合膜，将散热器附着的热界面材料放置在一个或多个部件上，将散热装置放置在 对应的一个或多个组件。

公开(公告)号：US07301227B1

公开(公告)日：2007-11-27

申请号：US11207630

申请日：2005-08-19

申请人： Vadim Gektin ,  Deviprasad Malladi

发明人： Vadim Gektin ,  Deviprasad Malladi

IPC分类号： H01L23/02 ,  H01L23/48

CPC分类号： H01L23/4006 ,  H01L23/04 ,  H01L23/3675 ,  H01L2023/405 ,  H01L2023/4062 ,  H01L2023/4081 ,  H01L2224/32245 ,  H01L2924/16152

摘要： A package for an integrated circuit (IC) die comprises a substrate and a lid. The substrate has an upper surface facing an interior of the package and a lower surface facing an exterior of the package. The upper surface of the substrate carries an IC die and provides electrical connections from the IC die to the lower surface of the substrate. The lid includes an outer lid and an inner lid. The inner lid is positioned over the IC die and is in thermal communication with the IC die. The inner lid is formed of a material suitable for conducting heat away from the IC die. The outer lid is attached to the upper surface of the substrate. A gap extends between the outer lid and inner lid.

摘要翻译： 用于集成电路（IC）管芯的封装包括衬底和盖子。 衬底具有面向封装内部的上表面和面向封装外部的下表面。 衬底的上表面承载IC管芯并且提供从IC管芯到衬底的下表面的电连接。 盖子包括外盖和内盖。 内盖位于IC芯片上方并与IC芯片热连通。 内盖由适于从IC芯片传导热量的材料形成。 外盖附接到基板的上表面。 间隙在外盖和内盖之间延伸。

公开(公告)号：US5972736A

公开(公告)日：1999-10-26

申请号：US205424

申请日：1998-12-04

申请人： Deviprasad Malladi ,  Mario J. Lee ,  Ehsan Ettehadieh ,  Nagaraj Mitty

发明人： Deviprasad Malladi ,  Mario J. Lee ,  Ehsan Ettehadieh ,  Nagaraj Mitty

IPC分类号： H01L23/24 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/24 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/181

摘要： An integrated circuit package with heat slug is disclosed. The heat slug is thermally coupled to one or more semiconductor die using a single layer of high conductivity adhesive. The assembly process of this invention includes the steps of initially attaching a temporary heat slug to the back side of a package body, to which one or more semiconductor die are attached. The semiconductor die are then electrically connected to the package body and encapsulated to maintain fixed positions within the package cavity. The temporary heat slug is then moved and a final heat slug is attached to the package body and the back side of the one or more semiconductor dies utilizing a single layer of high conductivity adhesive. The package is compact, has reduced complexity, and is inexpensive to manufacture.

摘要翻译： 公开了一种具有热塞的集成电路封装。 使用单层高导电性粘合剂将散热块热耦合到一个或多个半导体管芯。 本发明的组装方法包括以下步骤：将临时散热块附接到一个或多个半导体管芯附接到封装主体的背面。 然后将半导体管芯电连接到封装主体并封装以保持封装腔内的固定位置。 然后移动临时热块，并且使用单层高导电性粘合剂将最终的热块附着到封装主体和一个或多个半导体管芯的背面。 封装紧凑，复杂性降低，制造成本低廉。

公开(公告)号：US5528083A

公开(公告)日：1996-06-18

申请号：US317900

申请日：1994-10-04

申请人： Deviprasad Malladi ,  Eric L. Bogatin ,  Bahram Zand

发明人： Deviprasad Malladi ,  Eric L. Bogatin ,  Bahram Zand

IPC分类号： H01G4/33 ,  H01L21/60 ,  H01L21/822 ,  H01L23/495 ,  H01L23/50 ,  H01L23/64 ,  H01L27/04 ,  H01L23/12 ,  H01L23/14 ,  H01L23/522

CPC分类号： H01L24/06 ,  H01L23/49589 ,  H01L23/50 ,  H01L23/642 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  Y10S257/924

摘要： An integrated circuit chip and flat capacitor assembly are connected with short bonding wires to reduce electrical noise. A flat chip capacitor is coupled to the chip and includes a first electrode, a second electrode and a dielectric layer disposed between the electrodes. The ground and power bonding pads of an integrated circuit chip are coupled to a number of terminals arranged in a row near the outer edge of the capacitor, where each of the terminals is coupled to one of the electrodes. The terminals of the capacitor are connected to a number of package leads of a lead frame or a other integrated circuit package. The invention includes embodiments in which the chip is placed on top of the capacitor, the capacitor is placed on top of the chip, and a flex circuit of a micro ball grid array is placed on a capacitor which is positioned on a chip.

摘要翻译： 集成电路芯片和扁平电容器组件与短接合线连接以减少电气噪声。 扁平电容器耦合到芯片，并且包括设置在电极之间的第一电极，第二电极和介电层。 集成电路芯片的接地和电源接合焊盘被耦合到靠近电容器的外边缘排列成行的多个端子，其中每个端子耦合到电极中的一个。 电容器的端子连接到引线框架或其他集成电路封装的多个封装引线。 本发明包括其中将芯片放置在电容器顶部上的实施例，电容器放置在芯片的顶部，微球栅阵列的柔性电路放置在位于芯片上的电容器上。

公开(公告)号：US06636825B1

公开(公告)日：2003-10-21

申请号：US09364832

申请日：1999-07-30

申请人： Deviprasad Malladi ,  Renukanthan Raman ,  Christopher D. Furman

发明人： Deviprasad Malladi ,  Renukanthan Raman ,  Christopher D. Furman

IPC分类号： G01R3100

CPC分类号： G11C29/56016 ,  G01R31/2891 ,  G11C29/48

摘要： A method for performing electrical acceptance tests on a sub-system including a test substrate, a microprocessor and one or more associated computer components, such as SRAM, DRAM and ROM. A pin grid array, ball grid array, line grid array or equivalent test connector system is provided that allows direct addressing of selected circuits of the microprocessor and of each associated component. The microprocessor plus substrate are first tested together. If this test is successful, the associated components are then added, preferably one at a time, and the new sub-system is tested. If a particular sub-system fails a test, the cause(s) of failure can be isolated and removed, where possible, and the modified sub-system can be retested.

摘要翻译： 一种用于在包括测试基板，微处理器和一个或多个相关联的计算机组件（例如SRAM，DRAM和ROM）的子系统上进行电接受测试的方法。 提供了一种引脚网格阵列，球栅阵列，线阵列或等效测试连接器系统，其允许直接寻址微处理器和每个相关组件的选定电路。 首先在一起测试微处理器加衬底。 如果该测试成功，则相关组件然后被添加，最好一次添加，并且新的子系统被测试。 如果特定的子系统测试失败，则可能会将故障原因隔离并删除，并且可以重新测试修改后的子系统。

公开(公告)号：US06472900B1

公开(公告)日：2002-10-29

申请号：US09874188

申请日：2001-06-04

申请人： Deviprasad Malladi ,  Shahid Ansari ,  Hanxi Chen ,  Bidyut Sen ,  Steven Boyle

发明人： Deviprasad Malladi ,  Shahid Ansari ,  Hanxi Chen ,  Bidyut Sen ,  Steven Boyle

IPC分类号： G01R3126

CPC分类号： G01R1/0408 ,  H01L2224/73204 ,  H01L2924/15311

摘要： A method and system providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expos at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

摘要翻译： 一种提供具有至少两个信号处理层的集成半导体衬底的电测试的方法和系统。 衬底可以设置有塑料，硅，氧化硅，氮化硅等的保护层。 待电测试的一个衬底层的选定区域通过蚀刻或以其他方式形成可控制的小孔而暴露出任何覆盖的衬底层，以暴露所选区域中的至少一个所选择的电路迹线，并将所选择的电信号施加到 跟踪。 可选地，可以形成与第一孔间隔开的第二孔，以暴露第二选择的电路迹线，从而可以测试一个或多个衬底电路中的信号传播。 孔径横截面形状可以是线性或曲线多边形或其它合适的形状。

公开(公告)号：US5780930A

公开(公告)日：1998-07-14

申请号：US792088

申请日：1997-01-31

申请人： Deviprasad Malladi ,  Shahid S. Ansari ,  Eric Bogatin

发明人： Deviprasad Malladi ,  Shahid S. Ansari ,  Eric Bogatin

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/50 ,  H01L23/528 ,  H01L23/64 ,  H01L25/16 ,  H01L23/48 ,  H01G4/005 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/642 ,  H01L23/50 ,  H01L23/5286 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011

摘要： Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ("FIB"). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum. Conductive element pads are formed atop the conductive columnar elements at the outer surface of the IC passivation layer. The bypass capacitors are then attached to the IC, and the capacitor connecting pads are electrically connected to the respective conductive element pads using conductive epoxy or other conductive bond material. This direct attachment of the on-chip bypass capacitors reduces effective capacitance lead inductance and improves attenuation of on-chip switching noise.

摘要翻译： 通过最小化片上旁路电容的引线电感，降低集成电路VDD和VSS金属走线的开关噪声。 对于每个片上旁路电容器，形成一对带VDD和VSS的金属迹线，这些迹线具有横向间隔开的距离为对应于旁路电容器连接焊盘的横向分离的距离DELTA X的区域。 对于每个旁路电容器，根据需要通过钝化和金属间氧化物层形成间隔开的距离DELTA X的柱状开口。 这些开口暴露并接近承载VSS和VDD的一对间隔开的金属迹线的区域。 可以在IC制造之后形成的这些开口优选地使用聚焦离子束技术（“FIB”）形成。 或者，这些开口可以使用掩模和蚀刻步骤形成。 然后将柱状开口制成导电柱状元件，优选使用FIB沉积钨或铂。 导电元件焊盘形成在IC钝化层的外表面上的导电柱状元件顶上。 然后将旁路电容器附接到IC，并且电容器连接焊盘使用导电环氧树脂或其它导电粘合材料电连接到相应的导电元件焊盘。 片上旁路电容器的直接连接降低了有效的电容引线电感，并改善了片上开关噪声的衰减。

公开(公告)号：US20110256925A1

公开(公告)日：2011-10-20

申请号：US13014991

申请日：2011-01-27

申请人： John Schipani ,  Deviprasad Malladi

发明人： John Schipani ,  Deviprasad Malladi

IPC分类号： A63F9/24

CPC分类号： G07F17/3269 ,  G06Q50/34 ,  G07F17/32 ,  G07F17/3288

摘要： Methods, systems, and software for accepting bets on contests, such as sporting events, with wagering terms that change in real-time with the progress of the contests are disclosed. The disclosed methods, systems, and software may include security features that check the time at which bets are placed to ensure that they are not being placed in the interval between when an event occurred in the contest and when the wagering terms were changed to reflect that the event occurred.

摘要翻译： 公开了用于接受竞赛投注的方法，系统和软件，例如体育赛事，具有随比赛进度实时变化的下注条件。 公开的方法，系统和软件可以包括检查投注时间的安全特征，以确保它们不被放置在比赛中发生事件之间的时间间隔和当投注条件被改变以反映 事件发生了。

公开(公告)号：US06351389B1

公开(公告)日：2002-02-26

申请号：US08646426

申请日：1996-05-07

申请人： Deviprasad Malladi

发明人： Deviprasad Malladi

IPC分类号： H05K118

CPC分类号： H01L23/10 ,  H01L21/563 ,  H01L23/24 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

摘要： A method and apparatus for packaging an electronic device, such as an integrated circuit chip (8), includes an intermediate device carrier (6) with a substantially planar upper surface (16) and a plurality of bonding pads (18) for coupling the carrier to the integrated circuit chip. A ceramic ring (38) is attached to the upper surface of the device carrier and a thermally conductive cover plate (36) is attached to the ceramic ring to form an inner cavity for receiving the chip therein. The ceramic ring comprises a material with a coefficient of thermal expansion substantially similar to or as the same as the device carrier to minimize stress therebetween during thermal expansion or contraction of the package device. The thermally conductive cover plate provides a path for dissipating heat generated during electrical operations of the chip.

摘要翻译： 用于封装诸如集成电路芯片（8）的电子器件的方法和装置包括具有基本平坦的上表面（16）的中间器件载体（6）和用于将载体 到集成电路芯片。 陶瓷环（38）附着到器件载体的上表面，并且导热盖板（36）附接到陶瓷环上以形成用于在其中接收芯片的内腔。 陶瓷环包括具有与装置载体基本相似或相同的热膨胀系数的材料，以在包装装置的热膨胀或收缩期间最小化其间的应力。 导热盖板提供用于耗散芯片的电气操作期间产生的热量的路径。